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SOT2143-1[SOT2143-1]
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Bootable CPU RTC with Two I²C Buses, 128 Byte SRAM and Alarm Function
PCF85053A is a CMOS real-time clock (RTC) and calendar, optimized for low power consumption and automatic switching to battery on primary power loss. Featuring clock output, alert interrupt output and 128-byte battery backed-up SRAM, the PCF85053A includes two I²C buses. The primary I²C bus has the read / write capability on RTC and SRAM registers; the second I²C bus also can read / write most registers with the control bits set by primary I²C controller.
PCF85053A offers clock output calibration-related registers such as crystal capacitive load (CL) configuration and offset register setting.
Product Details
Features
Operating Voltage
- Supply voltage: 1.7 V to 3.6 V
- Battery supply voltage: 1.55 V to 3.6 V
Communication Interface
- Two independent I²C interfaces:
- Primary I²C bus: read / write capability on RTC and SRAM registers
- Second I²C bus: read / write capability on RTC and SRAM registers enabled by primary I²C
- I²C device addresses:
- RTC: 1101 111
- SRAM: 1010 111
- I²C clock features:
- Max CLK frequency 400 kHz
- Max CLK timeout 35 ms
- I²C bus not active when switch over to battery
Real Time Clock Features
- Real-time clock and calendar
- Provides year, month, day, weekday, hours, minutes and seconds based on a 32.768 kHz quartz crystal
- Support both binary mode and BCD mode
- Support 24-hour and 12-hour mode
- Support daylight saving mode
- Oscillator fail flag
- RTC clear flag
- RTC fail flag
- Alarm flag
Extra Features
- Active low alert interrupt output
- Register definition aligned to MC146818B (0 to 9 h)
- Configurable oscillator circuit for a wide variety of quartzes: CL = 6 pF, CL = 7 pF, and CL = 12.5 pF
- Operating temperature range -40 °C to 85 °C
- Battery-backed 128 byte SRAM
- SRAM clear to ‘0’ by RTC_CLR# pin
- Frequency adjustment via programmable offset register
Buy/Parametrics
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Documentation
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Evaluation and Development BoardsPCF85053ATK-ARD – PCF85053ATK Evaluation Board
