PowerQUICC® III Processor with DDR2/3, Pattern Matching Engine, PCI Express® | NXP Semiconductors

PowerQUICC® III Processor with DDR2/3, Pattern Matching Engine, PCI Express®

  • This page contains information on a product that is not recommended for new designs.
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Block Diagram

MPC8572 Block Diagram

Features

  • Dual e500 Power Architecture cores scaling to 1.5 GHz
  • 1 MB L2 cache/SRAM with I/O stashing
  • 32 KB I/D L1 cache per core
  • Dual integrated DDR2/DDR3 SDRAM memory controllers
    • 64-bits (72-bits with ECC) per controller
    • to 800 MHz datarate
  • Four integrated Ethernet controllers (enhanced TSEC)
    • 10/100/1000 support
    • TCP/UPD offload
    • Quality of service support
    • IEEE® 1588 support
    • Lossless flow control
    • SGMII interfaces
  • Single 10/100 fast Ethernet controller (FEC) with MII (muxed)
  • TLU offloading complex table searches
  • Pattern matching engine searches for regular expressions within packet payloads
    • Includes packet deflate engine to expose zipped payloads
  • Security engine
    • DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 encryption algorithms
  • PCI Express®
  • Serial RapidIO®
  • 32-bit local bus running up to 133 MHz
  • Dual I²C, Dual DMA, DUART, multiprocessor interrupt controller, IEEE1149.1 JTAG test access port
  • 1023-pin FC-PBGA package
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch

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N true 0 PSPMPC8572Een 59 Application Note Application Note t789 33 Application Note Software Application Note Software t783 3 Data Sheet Data Sheet t520 1 Fact Sheet Fact Sheet t523 1 Package Information Package Information t790 1 Quick Reference Guide Quick Reference Guide t525 1 Reference Manual Reference Manual t877 6 Supporting Information Supporting Information t531 2 User Guide User Guide t792 2 White Paper White Paper t530 9 en_US 3 1 4 English The MPC8572E family of processors is designed to offer clock speeds from 1.067 GHz up to 1.5 GHz, combining two powerful processor cores, enhanced peripherals and high-speed interconnect technology to balance processor performance with I/O system throughput. Based on the scalable e500 system-on-chip (SoC) platform built on Power Architecture &#174; technology, they deliver dual-core gigahertz-plus communications processing performance. 1153716175375698320991 PSP 258.1 KB None None documents None 1153716175375698320991 /docs/en/fact-sheet/MPC8572FS.pdf 258143 /docs/en/fact-sheet/MPC8572FS.pdf MPC8572FS N 2006-07-24 MPC8572E PowerQUICC<sup>&#174;</sup> &#174; III Processor - Fact Sheet /docs/en/fact-sheet/MPC8572FS.pdf /docs/en/fact-sheet/MPC8572FS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 pdf en Jan 31, 2008 Fact Sheet t523 Fact Sheet Fact Sheet Y N MPC8572E PowerQUICC<sup>&#174;</sup> &#174; III Processor - Fact Sheet 2 2 English This reference manual defines the functionality of the MPC8572E. This device integrates two PowerPC&#8482; processor cores, based on Power Architecture&#8482; technology, with system logic required for networking, telecommunications, and wireless infrastructure applications. 1184623419032690386458 PSP 16.2 MB None None documents None 1184623419032690386458 /docs/en/reference-manual/MPC8572ERM.pdf 16160528 /docs/en/reference-manual/MPC8572ERM.pdf MPC8572ERM N 2007-07-16 MPC8572E Reference Manual /docs/en/reference-manual/MPC8572ERM.pdf /docs/en/reference-manual/MPC8572ERM.pdf Reference Manual N Y 500633505221135046 2025-03-08 pdf en May 23, 2008 Reference Manual t877 Reference Manual Reference Manual Y N MPC8572E Reference Manual 3 7 English MPC8572EEC: This document describes the electrical characteristics of the MPC8572E PowerQUICC<sup>&#174;</sup> III integrated processor. 1215805936357717798138 PSP 1.1 MB None None documents None 1215805936357717798138 /docs/en/data-sheet/MPC8572EEC.pdf 1147485 /docs/en/data-sheet/MPC8572EEC.pdf MPC8572EEC N N 2008-07-11 MPC8572E PowerQUICC<sup>&#174;</sup> III Integrated Processor Hardware Specifications /docs/en/data-sheet/MPC8572EEC.pdf /docs/en/data-sheet/MPC8572EEC.pdf Data Sheet N Y 980000996212993340 2022-12-07 pdf N en Mar 1, 2016 Data Sheet t520 Data Sheet Data Sheet Y N MPC8572E PowerQUICC<sup>&#174;</sup> III Integrated Processor Hardware Specifications false en_US en Reference Manual Reference Manual 5 4 1 English This reference manual describes the resources defined for the Power ISA embedded environment. 1319210247754725815434 PSP 10.4 MB Registration without Disclaimer None documents Extended 1319210247754725815434 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 10448185 /secured/assets/documents/en/reference-manual/EREF_RM.pdf EREF_RM documents Y N 2016-10-31 EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /webapp/Download?colCode=EREF_RM /secured/assets/documents/en/reference-manual/EREF_RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jun 26, 2014 500633505221135046 Reference Manual Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 5 1.2 English E500CORER: This errata document describes corrections to the PowerPC &#8482; e500 Core Family Reference Manual, Revision 1. 1152820363245707387417 PSP 117.9 KB None None documents None 1152820363245707387417 /docs/en/reference-manual/e500CORERMAD.pdf 117856 /docs/en/reference-manual/e500CORERMAD.pdf E500CORERMAD documents N N 2016-10-31 E500CORER, Errata to PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/e500CORERMAD.pdf /docs/en/reference-manual/e500CORERMAD.pdf Reference Manual N 500633505221135046 2022-12-07 pdf N en Sep 11, 2012 500633505221135046 Reference Manual N E500CORER, Errata to PowerPC ™ e500 Core Family - Reference Manual 6 2.2 English This document describes corrections to the MPC8572E PowerQUICC<sup>&#174;</sup>&#8482; III Integrated Host Processor Reference Manual, Revision 2. 1211408868437728056062 PSP 563.5 KB None None documents None 1211408868437728056062 /docs/en/reference-manual/MPC8572ERMAD.pdf 563500 /docs/en/reference-manual/MPC8572ERMAD.pdf MPC8572ERMAD documents N 2008-05-21 Errata to MPC8572E PowerQUICC<sup>&#174;</sup>&#8482; III Integrated Processor Reference Manual, Rev. 2 /docs/en/reference-manual/MPC8572ERMAD.pdf /docs/en/reference-manual/MPC8572ERMAD.pdf Reference Manual N 500633505221135046 2022-12-07 pdf en Oct 14, 2009 500633505221135046 Reference Manual N N Errata to MPC8572E PowerQUICC<sup>&#174;</sup>&#8482; III Integrated Processor Reference Manual, Rev. 2 7 0 English Multicore devices provide a path forward for increased performance. This path requires comprehensive and pervasive system and software changes as well as new, innovative hardware designs to ensure that the software can take advantage of the increased computational power. NXP Semiconductors, Inc. has years of experience with many types of embedded multicore devices and thus can ensure that all necessary components are present to ease the software burden and to avoid having an inefficient core. This bala 1247173677125723218813 PSP 1.5 MB Registration without Disclaimer None documents Extended 1247173677125723218813 /secured/assets/documents/en/reference-manual/EMBMCRM.pdf 1486324 /secured/assets/documents/en/reference-manual/EMBMCRM.pdf EMBMCRM documents Y N 2016-10-31 Embedded Multicore: An Introduction /webapp/Download?colCode=EMBMCRM /secured/assets/documents/en/reference-manual/EMBMCRM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jul 20, 2009 500633505221135046 Reference Manual Y N Embedded Multicore: An Introduction 8 1 English The primary objective of this user&#8217;s manual is to describe the functionality of the e500 embedded microprocessor core for software and hardware developers. The e500 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the PowerPC architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words in the 64-bit general-purpose registers (GPRs). 111qmdXB PSP 5.7 MB None None documents None 111qmdXB /docs/en/reference-manual/E500CORERM.pdf 5707515 /docs/en/reference-manual/E500CORERM.pdf E500CORERM documents N 2016-10-31 PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/E500CORERM.pdf /docs/en/reference-manual/E500CORERM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf en May 11, 2005 500633505221135046 Reference Manual N PowerPC ™ e500 Core Family - Reference Manual Application Note Application Note 33 9 0 Chinese Reviewing the troubleshoot microcontroller when there is a malfunction module. 1641302649210707506203zh PSP 303.0 KB None None documents None 1641302649210707506203 /docs/zh/application-note/AN13461.pdf 302971 /docs/zh/application-note/AN13461.pdf AN13461 documents N N 2022-01-04 AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note /docs/zh/application-note/AN13461.pdf /docs/zh/application-note/AN13461.pdf Application Note N 645036621402383989 2022-12-07 zh May 9, 2022 645036621402383989 Application Note Y N 恩智浦微控制器故障排除清单 0 English Reviewing the troubleshoot microcontroller when there is a malfunction module. 1641302649210707506203 PSP 303.0 KB None None documents None 1641302649210707506203 /docs/en/application-note/AN13461.pdf 302971 /docs/en/application-note/AN13461.pdf AN13461 documents N N 2022-01-04 AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note /docs/en/application-note/AN13461.pdf /docs/en/application-note/AN13461.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 30, 2021 645036621402383989 Application Note Y N AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note 10 2 English Using the Core and System Performance Monitors 1493403864930712885479 PSP 278.3 KB Registration without Disclaimer None documents Extended 1493403864930712885479 /secured/assets/documents/en/application-note/AN3636.pdf 278345 /secured/assets/documents/en/application-note/AN3636.pdf AN3636 documents Y N 2017-04-28 PowerQUICC III Performance Monitors /webapp/Download?colCode=AN3636 /secured/assets/documents/en/application-note/AN3636.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Apr 28, 2017 645036621402383989 Application Note Y N PowerQUICC III Performance Monitors 11 3 English This document is a supplement to the SEC 2/3x reference device driver. 1224778148188710027580 PSP 1.1 MB Registration without Disclaimer None documents Extended 1224778148188710027580 /secured/assets/documents/en/application-note/AN3645.pdf 1147132 /secured/assets/documents/en/application-note/AN3645.pdf AN3645 documents Y N 2016-10-31 SEC 2/3x Descriptor Programmer’s Guide /webapp/Download?colCode=AN3645 /secured/assets/documents/en/application-note/AN3645.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Apr 28, 2017 645036621402383989 Application Note N SEC 2/3x Descriptor Programmer’s Guide 12 4 English AN4039: This application note expands on the description of the double data rate (DDR3) memory controller programmable registers in the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> processor reference manuals. 1264810112254717714233 PSP 468.7 KB None None documents None 1264810112254717714233 /docs/en/application-note/AN4039.pdf 468655 /docs/en/application-note/AN4039.pdf AN4039 documents N N 2016-10-31 AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note /docs/en/application-note/AN4039.pdf /docs/en/application-note/AN4039.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 11, 2014 645036621402383989 Application Note N AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note 13 11 English AN2583: This application note provides programming guidelines for the PowerQUICC<sup>&#174;</sup> DDR-SDRAM memory controller and specifically JEDEC-compatible DDR1 SDRAM memories. 1070297961506735248621 PSP 333.2 KB None None documents None 1070297961506735248621 /docs/en/application-note/AN2583.pdf 333170 /docs/en/application-note/AN2583.pdf AN2583 documents N N 2003-12-01 AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note /docs/en/application-note/AN2583.pdf /docs/en/application-note/AN2583.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jul 29, 2014 645036621402383989 Application Note Y N AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note 14 2 English This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. 1363012931515701443659 PSP 269.4 KB None None documents None 1363012931515701443659 /docs/en/application-note/AN4531.pdf 269380 /docs/en/application-note/AN4531.pdf AN4531 documents N N 2016-10-31 AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf /docs/en/application-note/AN4531.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Dec 16, 2013 645036621402383989 Application Note N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 15 6 English AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. 1264793052715706871063 PSP 547.7 KB Registration without Disclaimer None documents Extended 1264793052715706871063 /secured/assets/documents/en/application-note/AN3940.pdf 547662 /secured/assets/documents/en/application-note/AN3940.pdf AN3940 documents Y N 2016-10-31 AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /webapp/Download?colCode=AN3940 /secured/assets/documents/en/application-note/AN3940.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Nov 25, 2013 645036621402383989 Application Note Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 16 0 English This application note describes a procedure that allows users to validate the implementation of 1588-specific hardware in their system. 1309961595210675753552 PSP 743.2 KB None None documents None 1309961595210675753552 /docs/en/application-note/AN4326.pdf 743199 /docs/en/application-note/AN4326.pdf AN4326 documents N 2016-10-31 Verification of the IEEE 1588 Interface /docs/en/application-note/AN4326.pdf /docs/en/application-note/AN4326.pdf Application Note N 645036621402383989 2022-12-07 pdf en Jul 6, 2011 645036621402383989 Application Note N Verification of the IEEE 1588 Interface 17 Rev. 0 English This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. 1305312143395731535528 PSP 577.2 KB Registration without Disclaimer None documents Extended 1305312143395731535528 /secured/assets/documents/en/application-note/AN4311.pdf 577164 /secured/assets/documents/en/application-note/AN4311.pdf AN4311 documents Y N 2016-10-31 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /webapp/Download?colCode=AN4311 /secured/assets/documents/en/application-note/AN4311.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 13, 2011 645036621402383989 Application Note Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 18 0 English AN3830: This application note provides a practical guide to using Our CodeWarrior IDE to debug hardware. Focusing on PowerQUICC<sup>&#174;</sup> processors, this document covers many of the key features available in the IDE to assist in bring-up and troubleshooting of a new board. 1245429781973738421244 PSP 1.6 MB None None documents None 1245429781973738421244 /docs/en/application-note/AN3830.pdf 1576181 /docs/en/application-note/AN3830.pdf AN3830 documents N 2009-06-19 AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes /docs/en/application-note/AN3830.pdf /docs/en/application-note/AN3830.pdf Application Note N 645036621402383989 2022-12-07 pdf en Feb 1, 2011 645036621402383989 Application Note Y N AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes 19 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939 /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors 20 1 English This application note explains the contents of the leader device tree in a multicore Hypervisor implementation used to allocate system resources to the individual partitions.&#13;&#10;Additionally, it describes the contents of the individual device trees that each partition uses for local allocation of those resources. 1225213465876727613770 PSP 828.9 KB None None documents None 1225213465876727613770 /docs/en/application-note/AN3649.pdf 828938 /docs/en/application-note/AN3649.pdf AN3649 documents N N 2016-10-31 Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations /docs/en/application-note/AN3649.pdf /docs/en/application-note/AN3649.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Apr 19, 2010 645036621402383989 Application Note Y N Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations 21 0 English AN4064: This document explains how to enable and utilize 36-bit physical addressing. It describes the 36-bit capabilities of the e600 and e500v2, and later processor families. Addressing and memory management in a computer system is a difficult topic that is largely beyond the scope of this document. This section explains some of the basic concepts that are essential to understand in order to develop system-level software that utilizes 36-bit physical addressing. 1269842191514722596708 PSP 576.8 KB None None documents None 1269842191514722596708 /docs/en/application-note/AN4064.pdf 576818 /docs/en/application-note/AN4064.pdf AN4064 documents N 2016-10-31 AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes /docs/en/application-note/AN4064.pdf /docs/en/application-note/AN4064.pdf Application Note N 645036621402383989 2022-12-07 pdf en Mar 28, 2010 645036621402383989 Application Note N AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes 22 1 English This application note describes basic jitter terminology and the aspects pertaining to the SYSCLK clock design requirements. 1264143083962735811350 PSP 514.4 KB None None documents None 1264143083962735811350 /docs/en/application-note/AN4056.pdf 514364 /docs/en/application-note/AN4056.pdf AN4056 documents N 2016-10-31 Understanding SYSCLK Jitter /docs/en/application-note/AN4056.pdf /docs/en/application-note/AN4056.pdf Application Note N 645036621402383989 2022-12-07 pdf en Feb 18, 2010 645036621402383989 Application Note N Understanding SYSCLK Jitter 23 0 English AN4026SW.zip /secured/assets/documents/en/application-note-software/AN4026SW.zip /webapp/Download?colCode=AN4026SW&appType=license&docLang=en A common use of the QUICC Engine block is to establish an HDLC communication path over a TDM interface, such as a T1 or E1 link. This application note describes the various sub-blocks used in the QUICC Engine communications engine for this application, discusses how the sub-blocks interoperate with each other, describes how to initialize them for the HDLC communication path, and provides a software demonstration of HDLC mode via a TDM interface using on-chip loopback. 1260992898773711434436 PSP 718.0 KB None None documents None 1260992898773711434436 /docs/en/application-note/AN4026.pdf 718019 /docs/en/application-note/AN4026.pdf AN4026 documents N 2009-12-17 Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC /docs/en/application-note/AN4026.pdf /docs/en/application-note/AN4026.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 17, 2009 645036621402383989 Application Note N Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC 24 0 English High-level data link control (HDLC) is widely used in the telecommunications and networking industries. NXP&#8217;s PowerQUICC&#8482; communications processors have extensive support for HDLC protocol through the communications processor module (CPM) and QUICC Engine&#8482; technologies.&#13;&#10;&#13;&#10;This application note explains how NXP&#8217;s existing&#13;&#10;PowerQUICC communications processors use the CPM and QUICC Engine technologies to support the HDLC protocol and provides HDLC e 1258066893562722616236 PSP 496.6 KB None None documents None 1258066893562722616236 /docs/en/application-note/AN3966.pdf 496625 /docs/en/application-note/AN3966.pdf AN3966 documents N 2016-10-31 PowerQUICC™ HDLC Support and Example Code /docs/en/application-note/AN3966.pdf /docs/en/application-note/AN3966.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 10, 2009 645036621402383989 Application Note N PowerQUICC™ HDLC Support and Example Code 25 2 English NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. 1213738938672737755656 PSP 495.3 KB None None documents None 1213738938672737755656 /docs/en/application-note/AN3638.pdf 495318 /docs/en/application-note/AN3638.pdf AN3638 documents N N 2016-10-31 The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf /docs/en/application-note/AN3638.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Oct 26, 2009 645036621402383989 Application Note N The SystemID Format for Power Architecture™ Development Systems 26 0 English This document is an overview of how to configure&#13;&#10;PowerQUICC<sup>&#174;</sup> III and QorIQ<sup>&#174;</sup> P1xx/P2xx devices to boot from serial RapidIO&#8482; or PCI Express&#8482; with no additional boot flash/EEPROM. 1256145464773713684480 PSP 543.1 KB Registration without Disclaimer None documents Extended 1256145464773713684480 /secured/assets/documents/en/application-note/AN3646.pdf 543108 /secured/assets/documents/en/application-note/AN3646.pdf AN3646 documents Y N 2016-10-31 Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx /webapp/Download?colCode=AN3646 /secured/assets/documents/en/application-note/AN3646.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Oct 21, 2009 645036621402383989 Application Note N Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx 27 2 English This document provides recommendations for new designs based on the MPC8572E PowerQUICC<sup>&#174;</sup>&#8482; III family of integrated host communications processors. This document may also be useful in debugging newly designed systems by highlighting those aspects of a design that merit special attention during initial system startup. 1236958255534730670506 PSP 928.2 KB None None documents None 1236958255534730670506 /docs/en/application-note/AN3647.pdf 928238 /docs/en/application-note/AN3647.pdf AN3647 documents N 2009-03-13 MPC8572E PowerQUICC<sup>&#174;</sup>&#8482; III Bring-up Guide /docs/en/application-note/AN3647.pdf /docs/en/application-note/AN3647.pdf Application Note N 645036621402383989 2022-12-07 pdf en Jun 19, 2009 645036621402383989 Application Note Y N MPC8572E PowerQUICC<sup>&#174;</sup>&#8482; III Bring-up Guide 28 0 English This application note explains configuration&#13;&#10;requirements to assist users to successfully program and set up this interface type. It also compares SGMII to other gigabit Ethernet standards and interfaces. 1244236817778728476903 PSP 692.4 KB Registration without Disclaimer None documents Extended 1244236817778728476903 /secured/assets/documents/en/application-note/AN3869.pdf 692438 /secured/assets/documents/en/application-note/AN3869.pdf AN3869 documents Y N 2016-10-31 Implementing SGMII Interfaces on the PowerQUICC™ III /webapp/Download?colCode=AN3869 /secured/assets/documents/en/application-note/AN3869.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 5, 2009 645036621402383989 Application Note N Implementing SGMII Interfaces on the PowerQUICC™ III 29 0 English This application note explains the procedures to utilize the extra FC (Flow Control) credits for PCI Express inbound posted memory write transactions, which is currently a hidden feature for the Power QUICC III&#8482; devices. 1243968993550696784184 PSP 476.0 KB None None documents None 1243968993550696784184 /docs/en/application-note/AN3781.pdf 476033 /docs/en/application-note/AN3781.pdf AN3781 documents N 2010-05-11 Utilizing Extra FC Credits for PCI Express Inbound Posted Memory Write Transactions in PowerQUICC III&#8482; Devices /docs/en/application-note/AN3781.pdf /docs/en/application-note/AN3781.pdf Application Note N 645036621402383989 2022-12-07 pdf en Jun 2, 2009 645036621402383989 Application Note N Utilizing Extra FC Credits for PCI Express Inbound Posted Memory Write Transactions in PowerQUICC III&#8482; Devices 30 0 English AN3661SW.zip /docs/en/application-note-software/AN3661SW.zip /docs/en/application-note-software/AN3661SW.zip The following application note details a procedure for programming and resetting MSC8156 or MSC8144 StarCore<sup>&#174;</sup> DSPs over a serial RapidIO interface from an external host. 1231458979010730219558 PSP 655.6 KB None None documents None 1231458979010730219558 /docs/en/application-note/AN3661.pdf 655626 /docs/en/application-note/AN3661.pdf AN3661 documents N N 2016-10-31 RapidIO Technology in Wireless Base Stations: Programming DSPs over a RapidIO Interconnect /docs/en/application-note/AN3661.pdf /docs/en/application-note/AN3661.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jan 8, 2009 645036621402383989 Application Note N RapidIO Technology in Wireless Base Stations: Programming DSPs over a RapidIO Interconnect 31 1.0 English This application note describes an example of how to use an external DMA engine with a Serial RapidIO&#174; interface. 1208458263255715391554 PSP 505.7 KB None None documents None 1208458263255715391554 /docs/en/application-note/AN3550.pdf 505720 /docs/en/application-note/AN3550.pdf AN3550 documents N 2016-10-31 Using an External DMA Controller with Freescale Processors that Support Serial RapidIO® Technology /docs/en/application-note/AN3550.pdf /docs/en/application-note/AN3550.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 22, 2008 645036621402383989 Application Note N Using an External DMA Controller with Freescale Processors that Support Serial RapidIO® Technology 32 5.0 English This document expands on the description of the double data rate (DDR2) memory controller programmable registers described in the reference manuals for PowerQUICC processors. The corresponding material in the reference manual defines the function of each field in the programmable registers. This application note focuses when and why to select certain configurations of the bits and fields in the DDR2 registers to achieve efficient DDR programming. 1176147669904707686124 PSP 535.3 KB None None documents None 1176147669904707686124 /docs/en/application-note/AN3369.pdf 535277 /docs/en/application-note/AN3369.pdf AN3369 documents N 2007-04-09 PowerQUICC<sup>&#174;</sup> DDR2 SDRAM Controller Register Setting Considerations /docs/en/application-note/AN3369.pdf /docs/en/application-note/AN3369.pdf Application Note N 645036621402383989 2022-12-07 pdf en Sep 11, 2008 645036621402383989 Application Note Y N PowerQUICC<sup>&#174;</sup> DDR2 SDRAM Controller Register Setting Considerations 33 0 English AN3542: This application note discusses the differences between SMP and AMP (asymmetric multi-processor) OSs, booting options and features of the MPC8572E, and configuration of shared and non-shared resources between cores. This application note also provides a description of the boot process implemented by Uboot and Linux that is provided as part of the MPC8572E development system board support package. 1202329207598722883383 PSP 519.9 KB None None documents None 1202329207598722883383 /docs/en/application-note/AN3542.pdf 519909 /docs/en/application-note/AN3542.pdf AN3542 documents N 2016-10-31 AN3542, SMP Boot Process for Dual E500 Cores - Application Notes /docs/en/application-note/AN3542.pdf /docs/en/application-note/AN3542.pdf Application Note N 645036621402383989 2022-12-07 pdf en Jan 25, 2008 645036621402383989 Application Note N AN3542, SMP Boot Process for Dual E500 Cores - Application Notes 34 0 English This application note provides an overview and specific strategies for cache coherency and potential performance impacts in the PowerQUICC<sup>&#174;</sup> II Pro and PowerQUICC III families. It focuses on data coherency and potential system issues, as well as some concerns associated with having multiple DMA devices. It also discusses the specific steps and interdependencies required to implement hardware enforced cache coherency. 1198270786976715604383 PSP 547.7 KB None None documents None 1198270786976715604383 /docs/en/application-note/AN3544.pdf 547694 /docs/en/application-note/AN3544.pdf AN3544 documents N 2016-10-31 PowerQUICC™ Data Cache Coherency /docs/en/application-note/AN3544.pdf /docs/en/application-note/AN3544.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 21, 2007 645036621402383989 Application Note N PowerQUICC™ Data Cache Coherency 35 1 English This document describes aspects of memory synchronization and cache coherency requirements for NXP&#8217;s PowerQUICC<sup>&#174;</sup>&#8482; III product family. Coherency and synchronization need be considered, both for data and instructions, when initializing memory or moving memory contents from one location to another. 1191253168152709402147 PSP 189.0 KB None None documents None 1191253168152709402147 /docs/en/application-note/AN3441.pdf 188954 /docs/en/application-note/AN3441.pdf AN3441 documents N 2016-10-31 Coherency and Synchronization Requirements for PowerQUICC™ III /docs/en/application-note/AN3441.pdf /docs/en/application-note/AN3441.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 17, 2007 645036621402383989 Application Note N Coherency and Synchronization Requirements for PowerQUICC™ III 36 1 English The enhanced three-speed Ethernet controller (eTSEC) offered on many PowerQUICC&#8482; II Pro, PowerQUICC&#8482; III, and other devices, allows for flexible manipulation of incoming and outgoing Ethernet data. One such feature is the ability to receive and propagate padded, or &#8220;shimmed,&#8221; OSI layer 2 data to accommodate custom routing or direction of Ethernet data within a network. This application note describes what the shimming functionality does and the details of how to best utilize it. 1196114880779719950774 PSP 497.2 KB None None documents None 1196114880779719950774 /docs/en/application-note/AN3537.pdf 497175 /docs/en/application-note/AN3537.pdf AN3537 documents N 2016-10-31 Accommodating Layer 2 Padding (Shimming) with the Enhanced Three-Speed Ethernet Controller (eTSEC) /docs/en/application-note/AN3537.pdf /docs/en/application-note/AN3537.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 6, 2007 645036621402383989 Application Note N Accommodating Layer 2 Padding (Shimming) with the Enhanced Three-Speed Ethernet Controller (eTSEC) 37 0 English This application note provides an introduction to the error correcting code (ECC) technology as well as an aid to initialization and error recovery on Our PowerQUICC<sup>&#174;</sup> III family of processors. 1196228463425717224884 PSP 573.0 KB None None documents None 1196228463425717224884 /docs/en/application-note/AN3532.pdf 572952 /docs/en/application-note/AN3532.pdf AN3532 documents N 2016-10-31 Error Correction and Error Handling on PowerQUICC (TM) III Processors /docs/en/application-note/AN3532.pdf /docs/en/application-note/AN3532.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 27, 2007 645036621402383989 Application Note N Error Correction and Error Handling on PowerQUICC (TM) III Processors 38 0 English This application note explains how to program one of the eLBC&#8217;s user-programmable machines (UPMs) to control an SDRAM memory device. 1194558645992741221612 PSP 574.8 KB None None documents None 1194558645992741221612 /docs/en/application-note/AN3533.pdf 574761 /docs/en/application-note/AN3533.pdf AN3533 documents N 2007-11-08 Programming the User-Programmable Machine (UPM) for SDRAM Memory Devices /docs/en/application-note/AN3533.pdf /docs/en/application-note/AN3533.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 8, 2007 645036621402383989 Application Note Y N Programming the User-Programmable Machine (UPM) for SDRAM Memory Devices 39 0 English AN3445: This application note outlines general, high-level, architectural differences between the e300 and e500 family processors. The e300 family (which are based on the original 603 design) was designed to the original PowerPC architecture definition. The e500v1 and e500v2 processors are designed to what was originally the PowerPC Book E architecture and NXP?s embedded implementation standards (EIS). 1194389310604697206738 PSP 935.0 KB None None documents None 1194389310604697206738 /docs/en/application-note/AN3445.pdf 934951 /docs/en/application-note/AN3445.pdf AN3445 documents N 2016-10-31 AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3445.pdf /docs/en/application-note/AN3445.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 31, 2007 645036621402383989 Application Note N AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes 40 0 English AN3531: This application note outlines general, high-level, architectural differences between the e600 and e500 family processors. Is intended as a general guideline for programmers and system designers who are assessing the efforts required in migrating to e500-based devices. 1194389312415718217914 PSP 961.6 KB None None documents None 1194389312415718217914 /docs/en/application-note/AN3531.pdf 961596 /docs/en/application-note/AN3531.pdf AN3531 documents N N 2016-10-31 AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3531.pdf /docs/en/application-note/AN3531.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Oct 31, 2007 645036621402383989 Application Note N AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes 41 2 English These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. 1128961595061725581551 PSP 619.7 KB None None documents None 1128961595061725581551 /docs/en/application-note/AN2910.pdf 619650 /docs/en/application-note/AN2910.pdf AN2910 documents N 2016-10-31 Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf /docs/en/application-note/AN2910.pdf Application Note N 645036621402383989 2022-12-07 pdf en Mar 27, 2007 645036621402383989 Application Note N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces User Guide User Guide 2 42 1 English MPC8572DS is a high-performance computing, evaluation and development platform supporting the MPC8572 processor built on Power Architecture technology. 1208892472886723833004 PSP 1.1 MB None None documents None 1208892472886723833004 /docs/en/user-guide/MPC8572DSUG.pdf 1114979 /docs/en/user-guide/MPC8572DSUG.pdf MPC8572DSUG documents N 2008-04-22 MPC8572 Development System User&#8217;s Guide /docs/en/user-guide/MPC8572DSUG.pdf /docs/en/user-guide/MPC8572DSUG.pdf User Guide N 132339537837198660 2023-06-18 pdf en Jan 12, 2009 132339537837198660 User Guide Y N MPC8572 Development System User&#8217;s Guide 43 2.1 English This document describes the known errata and limitations of the Whitefin Development System. In all cases, if an errata has a work-around, it is applied to the system before shipped to customers. 1210970430129731816114 PSP 486.1 KB None None documents None 1210970430129731816114 /docs/en/user-guide/MPC8572DSBE.pdf 486061 /docs/en/user-guide/MPC8572DSBE.pdf MPC8572DSBE documents N 2008-05-16 MPC8572DS (Whitefin) Development System Errata /docs/en/user-guide/MPC8572DSBE.pdf /docs/en/user-guide/MPC8572DSBE.pdf User Guide N 132339537837198660 2023-06-18 pdf en Apr 11, 2008 132339537837198660 User Guide Y N MPC8572DS (Whitefin) Development System Errata Application Note Software Application Note Software 3 44 0 English 1258066894053701788655 PSP 330.9 KB Registration With Click-Thru Software Licensing Agreement 1395958162559706127527 documents Extended 1258066894053701788655 /secured/assets/documents/en/application-note-software/AN3966SW.zip 330857 /secured/assets/documents/en/application-note-software/AN3966SW.zip AN3966SW documents Y N 2016-10-31 Software to accompany application note AN3966 /webapp/Download?colCode=AN3966SW&appType=license /secured/assets/documents/en/application-note-software/AN3966SW.zip Application Note Software N 789425793691620447 2022-12-07 zip Y en Nov 10, 2009 789425793691620447 Application Note Software N Software to accompany application note AN3966 45 0 English 1231523385210702386268 PSP 7.4 KB None None documents None 1231523385210702386268 /docs/en/application-note-software/AN3661SW.zip 7354 /docs/en/application-note-software/AN3661SW.zip AN3661SW documents N 2009-01-09 AN3661 Associated Software /docs/en/application-note-software/AN3661SW.zip /docs/en/application-note-software/AN3661SW.zip Application Note Software N 789425793691620447 2022-12-07 zip en Jan 8, 2009 789425793691620447 Application Note Software D N AN3661 Associated Software 46 0 English This application note looks at the use of the NXP regular expression pattern matching engine (PME) along with its stateful rules to enable content processing of SIP messages at gigabit rates. 1185652886394699344557 PSP 160.2 KB None None documents None 1185652886394699344557 /docs/en/application-note-software/AN3432.pdf 160216 /docs/en/application-note-software/AN3432.pdf AN3432 documents N 2007-07-28 PowerQUICC<sup>&#174;</sup> SIP Firewall Traversal: Using NXP<sup>&#174;</sup> Stateful Rules /docs/en/application-note-software/AN3432.pdf /docs/en/application-note-software/AN3432.pdf Application Note Software N 789425793691620447 2022-12-07 pdf en Jul 28, 2007 789425793691620447 Application Note Software D N PowerQUICC<sup>&#174;</sup> SIP Firewall Traversal: Using NXP<sup>&#174;</sup> Stateful Rules Package Information Package Information 1 47 1 English This document is a presentation on understanding the FC-PBGA package. 1273780789511716723050 PSP 5.2 MB None None documents None 1273780789511716723050 /docs/en/package-information/FC-PBGAPRES.pdf 5219387 /docs/en/package-information/FC-PBGAPRES.pdf FC-PBGAPRES documents N N 2016-10-31 Flip Chip Plastic Ball Grid Array (FC-PBGA) Presentation /docs/en/package-information/FC-PBGAPRES.pdf /docs/en/package-information/FC-PBGAPRES.pdf Package Information N 302435339416912908 2022-12-07 pdf N en Jul 8, 2015 302435339416912908 Package Information N Flip Chip Plastic Ball Grid Array (FC-PBGA) Presentation Quick Reference Guide Quick Reference Guide 1 48 0 English 1202161387706708958941 PSP 279.7 KB None None documents None 1202161387706708958941 /docs/en/quick-reference-guide/MPC8572ECFG.pdf 279698 /docs/en/quick-reference-guide/MPC8572ECFG.pdf MPC8572ECFG documents N 2008-02-04 MPC8572DS Development System Configuration Guide /docs/en/quick-reference-guide/MPC8572ECFG.pdf /docs/en/quick-reference-guide/MPC8572ECFG.pdf Quick Reference Guide N 803735842453594974 2022-12-07 pdf en Oct 30, 2007 803735842453594974 Quick Reference Guide Y N MPC8572DS Development System Configuration Guide Supporting Information Supporting Information 2 49 1.9 English FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. 1368836090577704535160 PSP 303.5 KB None None documents None 1368836090577704535160 /docs/en/supporting-information/FSLNISTCAVP.pdf 303546 /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP documents N N 2016-11-09 FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf /docs/en/supporting-information/FSLNISTCAVP.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 28, 2016 371282830530968666 Supporting Information Y N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 50 1 English Customer Export Control Information Document 1232680175270712682745 PSP 21.4 KB None None documents None 1232680175270712682745 /docs/en/supporting-information/MPC8572EFAMPECI.pdf 21417 /docs/en/supporting-information/MPC8572EFAMPECI.pdf MPC8572EFAMPECI documents N N 2016-10-31 MPC8572E Family Customer Export Control Information /docs/en/supporting-information/MPC8572EFAMPECI.pdf /docs/en/supporting-information/MPC8572EFAMPECI.pdf Supporting Information N 371282830530968666 2023-06-19 pdf N en Dec 10, 2010 371282830530968666 Supporting Information Y N MPC8572E Family Customer Export Control Information White Paper White Paper 9 51 3 English Network security protocols and applications use a variety of cryptographic algorithms to achieve these high-level goals. Because cryptography is computationally intensive, hardware acceleration is highly desirable when cryptographic algorithms are frequent system functions. 1227561595497709456436 PSP 580.1 KB Registration without Disclaimer None documents Extended 1227561595497709456436 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf 580121 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf CRYPTOWP documents Y N 2016-10-31 Understanding Cryptographic Performance /webapp/Download?colCode=CRYPTOWP /secured/assets/documents/en/white-paper/CRYPTOWP.pdf White Paper N 918633085541740938 2022-12-07 pdf Y en Aug 15, 2008 918633085541740938 White Paper Y N Understanding Cryptographic Performance 52 0 English The focus of this white paper is to provide the end user with high level design considerations and/or trade-offs associated with migrating from SDRAM to DDR SDRAM-based designs. 1208376896761708228520 PSP 735.3 KB None None documents None 1208376896761708228520 /docs/en/white-paper/DDRSDRAMWP.pdf 735286 /docs/en/white-paper/DDRSDRAMWP.pdf DDRSDRAMWP documents N N 2016-10-31 Comparison of DDRx and SDRAM /docs/en/white-paper/DDRSDRAMWP.pdf /docs/en/white-paper/DDRSDRAMWP.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Apr 16, 2008 918633085541740938 White Paper Y N Comparison of DDRx and SDRAM 53 1 English NXP&#8217;s next-generation Multi-core Communications Platform is an innovative evolution of our established&#13;&#10;PowerQUICC<sup>&#174;</sup> architecture designed to enable a new era of networking where the reliability, security and quality of&#13;&#10;service for every connection matters. This white paper introduces you to the technical architecture of this platform&#13;&#10;and its comprehensive approach to solving the programmability problem. 1182464945682712255909 PSP 318.0 KB None None documents None 1182464945682712255909 /docs/en/white-paper/MULTICOREFTFWP.pdf 317969 /docs/en/white-paper/MULTICOREFTFWP.pdf MULTICOREFTFWP documents N 2007-06-21 A Smarter Approach to Multi-Core: NXP&#8217;s Next-Generation Communications Platform /docs/en/white-paper/MULTICOREFTFWP.pdf /docs/en/white-paper/MULTICOREFTFWP.pdf White Paper N 918633085541740938 2023-06-19 pdf en Jan 31, 2008 918633085541740938 White Paper Y N A Smarter Approach to Multi-Core: NXP&#8217;s Next-Generation Communications Platform 54 0 English In this white paper, we will use the term "application-aware networking" to refer to the function of network nodes processing application layer protocol and content &#8211; in addition to packet header &#8211; in order to perform the networking features they are designed to provide. This white paper describes how high-performance, cost-effective application-aware networking equipment can be designed with the MPC8572E. 1170362096385722242536 PSP 845.0 KB None None documents None 1170362096385722242536 /docs/en/white-paper/MPC8572EWP.pdf 845007 /docs/en/white-paper/MPC8572EWP.pdf MPC8572EWP documents N 2007-02-01 Designing Application-Aware Networking Equipment with the PowerQUICC<sup>&#174;</sup> III MPC8572E /docs/en/white-paper/MPC8572EWP.pdf /docs/en/white-paper/MPC8572EWP.pdf White Paper N 918633085541740938 2023-06-19 pdf en Jun 15, 2007 918633085541740938 White Paper Y N Designing Application-Aware Networking Equipment with the PowerQUICC<sup>&#174;</sup> III MPC8572E 55 0 English 1182279281048723030722 PSP 301.4 KB None None documents None 1182279281048723030722 /docs/en/white-paper/PQMPC8572EWP.pdf 301430 /docs/en/white-paper/PQMPC8572EWP.pdf PQMPC8572EWP documents N 2007-06-19 Designing IDS/IPS with the PowerQUICC<sup>&#174;</sup>&#174; III MPC8572E /docs/en/white-paper/PQMPC8572EWP.pdf /docs/en/white-paper/PQMPC8572EWP.pdf White Paper N 918633085541740938 2023-06-19 pdf en Jun 15, 2007 918633085541740938 White Paper Y N Designing IDS/IPS with the PowerQUICC<sup>&#174;</sup>&#174; III MPC8572E 56 0 English 1182279283464714008667 PSP 361.2 KB None None documents None 1182279283464714008667 /docs/en/white-paper/UTMMPC8572EWP.pdf 361209 /docs/en/white-paper/UTMMPC8572EWP.pdf UTMMPC8572EWP documents N 2007-06-19 Designing UTM with the PowerQUICC<sup>&#174;</sup>&#174; III MPC8572E /docs/en/white-paper/UTMMPC8572EWP.pdf /docs/en/white-paper/UTMMPC8572EWP.pdf White Paper N 918633085541740938 2023-06-19 pdf en Jun 15, 2007 918633085541740938 White Paper Y N Designing UTM with the PowerQUICC<sup>&#174;</sup>&#174; III MPC8572E 57 0 English The stateful inspection firewall/IPSec VPN security gateway has been&#8212;and still is&#8212;the most critical piece of network security equipment for most enterprises. Firewall/VPN is a perimeter-defense device, typically deployed where the enterprise&#8217;s internal network meets the open Internet. This white paper focuses on describing how the MPC8572E can be used for firewall/VPN design. 1170362082872730223398 PSP 888.8 KB None None documents None 1170362082872730223398 /docs/en/white-paper/FIREWALLVPNWP.pdf 888797 /docs/en/white-paper/FIREWALLVPNWP.pdf FIREWALLVPNWP documents N 2007-02-01 Designing Firewall/VPN with the PowerQUICC<sup>&#174;</sup> III MPC8572E /docs/en/white-paper/FIREWALLVPNWP.pdf /docs/en/white-paper/FIREWALLVPNWP.pdf White Paper N 918633085541740938 2022-12-07 pdf en Jun 15, 2007 918633085541740938 White Paper Y N Designing Firewall/VPN with the PowerQUICC<sup>&#174;</sup> III MPC8572E 58 1 English Accelerated Anti-Virus (Accelerated AV) is a high-performance network anti-virus solution platform jointly offered by Kaspersky Lab (Kaspersky) and NXP Semiconductors, Inc. (NXP) to OEM vendors. Accelerated AV is based on NXP&#8217;s MPC8572E PowerQUICC<sup>&#174;</sup> III processor and Kaspersky&#8217;s SafeStream signatures database. 1170362100151719945730 PSP 637.8 KB None None documents None 1170362100151719945730 /docs/en/white-paper/KASPERSKYWP.pdf 637783 /docs/en/white-paper/KASPERSKYWP.pdf KASPERSKYWP documents N 2007-02-01 NXP<sup>&#174;</sup>-Kaspersky Accelerated Antivirus Solution Platform for OEM Vendors /docs/en/white-paper/KASPERSKYWP.pdf /docs/en/white-paper/KASPERSKYWP.pdf White Paper N 918633085541740938 2023-06-19 pdf en Jun 15, 2007 918633085541740938 White Paper Y N NXP<sup>&#174;</sup>-Kaspersky Accelerated Antivirus Solution Platform for OEM Vendors 59 0 English white paper 1106677389248718091991 PSP 115.6 KB None None documents None 1106677389248718091991 /docs/en/white-paper/multicoreWP.pdf 115647 /docs/en/white-paper/multicoreWP.pdf MULTICOREWP documents N 2005-01-25 Multi-Core Microprocessors in Embedded Applications /docs/en/white-paper/multicoreWP.pdf /docs/en/white-paper/multicoreWP.pdf White Paper N 918633085541740938 2023-06-19 pdf en Jan 25, 2005 918633085541740938 White Paper Y N Multi-Core Microprocessors in Embedded Applications false 0 MPC8572E downloads en true 1 Y PSP Application Note 33 /docs/en/application-note/AN13461.pdf 2022-01-04 1641302649210707506203 PSP 9 Nov 30, 2021 Application Note Reviewing the troubleshoot microcontroller when there is a malfunction module. None /docs/en/application-note/AN13461.pdf English documents 302971 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN13461.pdf AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note /docs/en/application-note/AN13461.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note 303.0 KB AN13461 N 1641302649210707506203 /secured/assets/documents/en/application-note/AN3636.pdf 2017-04-28 1493403864930712885479 PSP 10 Apr 28, 2017 Application Note Using the Core and System Performance Monitors Registration without Disclaimer /secured/assets/documents/en/application-note/AN3636.pdf English documents 278345 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3636 PowerQUICC III Performance Monitors /secured/assets/documents/en/application-note/AN3636.pdf documents 645036621402383989 Application Note N en Extended Y pdf 2 Y N PowerQUICC III Performance Monitors 278.3 KB AN3636 N 1493403864930712885479 /secured/assets/documents/en/application-note/AN3645.pdf 2016-10-31 1224778148188710027580 PSP 11 Apr 28, 2017 Application Note This document is a supplement to the SEC 2/3x reference device driver. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3645.pdf English documents 1147132 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3645 SEC 2/3x Descriptor Programmer’s Guide /secured/assets/documents/en/application-note/AN3645.pdf documents 645036621402383989 Application Note N en Extended pdf 3 Y N SEC 2/3x Descriptor Programmer’s Guide 1.1 MB AN3645 N 1224778148188710027580 /docs/en/application-note/AN4039.pdf 2016-10-31 1264810112254717714233 PSP 12 Nov 11, 2014 Application Note AN4039: This application note expands on the description of the double data rate (DDR3) memory controller programmable registers in the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> processor reference manuals. None /docs/en/application-note/AN4039.pdf English documents 468655 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4039.pdf AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note /docs/en/application-note/AN4039.pdf documents 645036621402383989 Application Note N en None pdf 4 N N AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note 468.7 KB AN4039 N 1264810112254717714233 /docs/en/application-note/AN2583.pdf 2003-12-01 1070297961506735248621 PSP 13 Jul 29, 2014 Application Note AN2583: This application note provides programming guidelines for the PowerQUICC<sup>&#174;</sup> DDR-SDRAM memory controller and specifically JEDEC-compatible DDR1 SDRAM memories. None /docs/en/application-note/AN2583.pdf English documents 333170 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN2583.pdf AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note /docs/en/application-note/AN2583.pdf documents 645036621402383989 Application Note N en None Y pdf 11 N N AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note 333.2 KB AN2583 N 1070297961506735248621 /docs/en/application-note/AN4531.pdf 2016-10-31 1363012931515701443659 PSP 14 Dec 16, 2013 Application Note This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. None /docs/en/application-note/AN4531.pdf English documents 269380 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4531.pdf AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf documents 645036621402383989 Application Note N en None pdf 2 N N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 269.4 KB AN4531 N 1363012931515701443659 /secured/assets/documents/en/application-note/AN3940.pdf 2016-10-31 1264793052715706871063 PSP 15 Nov 25, 2013 Application Note AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3940.pdf English documents 547662 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3940 AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /secured/assets/documents/en/application-note/AN3940.pdf documents 645036621402383989 Application Note N en Extended Y pdf 6 Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 547.7 KB AN3940 N 1264793052715706871063 /docs/en/application-note/AN4326.pdf 2016-10-31 1309961595210675753552 PSP 16 Jul 6, 2011 Application Note This application note describes a procedure that allows users to validate the implementation of 1588-specific hardware in their system. None /docs/en/application-note/AN4326.pdf English documents 743199 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4326.pdf Verification of the IEEE 1588 Interface /docs/en/application-note/AN4326.pdf documents 645036621402383989 Application Note N en None pdf 0 N Verification of the IEEE 1588 Interface 743.2 KB AN4326 N 1309961595210675753552 /secured/assets/documents/en/application-note/AN4311.pdf 2016-10-31 1305312143395731535528 PSP 17 May 13, 2011 Application Note This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4311.pdf English documents 577164 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4311 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /secured/assets/documents/en/application-note/AN4311.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev. 0 Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 577.2 KB AN4311 N 1305312143395731535528 /docs/en/application-note/AN3830.pdf 2009-06-19 1245429781973738421244 PSP 18 Feb 1, 2011 Application Note AN3830: This application note provides a practical guide to using Our CodeWarrior IDE to debug hardware. Focusing on PowerQUICC<sup>&#174;</sup> processors, this document covers many of the key features available in the IDE to assist in bring-up and troubleshooting of a new board. None /docs/en/application-note/AN3830.pdf English documents 1576181 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3830.pdf AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes /docs/en/application-note/AN3830.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes 1.6 MB AN3830 N 1245429781973738421244 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 19 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939 DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 /docs/en/application-note/AN3649.pdf 2016-10-31 1225213465876727613770 PSP 20 Apr 19, 2010 Application Note This application note explains the contents of the leader device tree in a multicore Hypervisor implementation used to allocate system resources to the individual partitions.&#13;&#10;Additionally, it describes the contents of the individual device trees that each partition uses for local allocation of those resources. None /docs/en/application-note/AN3649.pdf English documents 828938 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3649.pdf Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations /docs/en/application-note/AN3649.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations 828.9 KB AN3649 N 1225213465876727613770 /docs/en/application-note/AN4064.pdf 2016-10-31 1269842191514722596708 PSP 21 Mar 28, 2010 Application Note AN4064: This document explains how to enable and utilize 36-bit physical addressing. It describes the 36-bit capabilities of the e600 and e500v2, and later processor families. Addressing and memory management in a computer system is a difficult topic that is largely beyond the scope of this document. This section explains some of the basic concepts that are essential to understand in order to develop system-level software that utilizes 36-bit physical addressing. None /docs/en/application-note/AN4064.pdf English documents 576818 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4064.pdf AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes /docs/en/application-note/AN4064.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes 576.8 KB AN4064 N 1269842191514722596708 /docs/en/application-note/AN4056.pdf 2016-10-31 1264143083962735811350 PSP 22 Feb 18, 2010 Application Note This application note describes basic jitter terminology and the aspects pertaining to the SYSCLK clock design requirements. None /docs/en/application-note/AN4056.pdf English documents 514364 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4056.pdf Understanding SYSCLK Jitter /docs/en/application-note/AN4056.pdf documents 645036621402383989 Application Note N en None pdf 1 N Understanding SYSCLK Jitter 514.4 KB AN4056 N 1264143083962735811350 /docs/en/application-note/AN4026.pdf 2009-12-17 1260992898773711434436 PSP 23 Dec 17, 2009 Application Note A common use of the QUICC Engine block is to establish an HDLC communication path over a TDM interface, such as a T1 or E1 link. This application note describes the various sub-blocks used in the QUICC Engine communications engine for this application, discusses how the sub-blocks interoperate with each other, describes how to initialize them for the HDLC communication path, and provides a software demonstration of HDLC mode via a TDM interface using on-chip loopback. None /docs/en/application-note/AN4026.pdf English documents 718019 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4026.pdf Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC /docs/en/application-note/AN4026.pdf documents 645036621402383989 Application Note N en None pdf 0 N Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC 718.0 KB AN4026 N 1260992898773711434436 /docs/en/application-note/AN3966.pdf 2016-10-31 1258066893562722616236 PSP 24 Nov 10, 2009 Application Note High-level data link control (HDLC) is widely used in the telecommunications and networking industries. NXP&#8217;s PowerQUICC&#8482; communications processors have extensive support for HDLC protocol through the communications processor module (CPM) and QUICC Engine&#8482; technologies.&#13;&#10;&#13;&#10;This application note explains how NXP&#8217;s existing&#13;&#10;PowerQUICC communications processors use the CPM and QUICC Engine technologies to support the HDLC protocol and provides HDLC e None /docs/en/application-note/AN3966.pdf English documents 496625 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3966.pdf PowerQUICC™ HDLC Support and Example Code /docs/en/application-note/AN3966.pdf documents 645036621402383989 Application Note N en None pdf 0 N PowerQUICC™ HDLC Support and Example Code 496.6 KB AN3966 N 1258066893562722616236 /docs/en/application-note/AN3638.pdf 2016-10-31 1213738938672737755656 PSP 25 Oct 26, 2009 Application Note NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. None /docs/en/application-note/AN3638.pdf English documents 495318 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3638.pdf The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf documents 645036621402383989 Application Note N en None pdf 2 N N The SystemID Format for Power Architecture™ Development Systems 495.3 KB AN3638 N 1213738938672737755656 /secured/assets/documents/en/application-note/AN3646.pdf 2016-10-31 1256145464773713684480 PSP 26 Oct 21, 2009 Application Note This document is an overview of how to configure&#13;&#10;PowerQUICC<sup>&#174;</sup> III and QorIQ<sup>&#174;</sup> P1xx/P2xx devices to boot from serial RapidIO&#8482; or PCI Express&#8482; with no additional boot flash/EEPROM. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3646.pdf English documents 543108 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3646 Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx /secured/assets/documents/en/application-note/AN3646.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx 543.1 KB AN3646 N 1256145464773713684480 /docs/en/application-note/AN3647.pdf 2009-03-13 1236958255534730670506 PSP 27 Jun 19, 2009 Application Note This document provides recommendations for new designs based on the MPC8572E PowerQUICC<sup>&#174;</sup>&#8482; III family of integrated host communications processors. This document may also be useful in debugging newly designed systems by highlighting those aspects of a design that merit special attention during initial system startup. None /docs/en/application-note/AN3647.pdf English documents 928238 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3647.pdf MPC8572E PowerQUICC<sup>&#174;</sup>&#8482; III Bring-up Guide /docs/en/application-note/AN3647.pdf documents 645036621402383989 Application Note N en None Y pdf 2 N MPC8572E PowerQUICC<sup>&#174;</sup>&#8482; III Bring-up Guide 928.2 KB AN3647 N 1236958255534730670506 /secured/assets/documents/en/application-note/AN3869.pdf 2016-10-31 1244236817778728476903 PSP 28 Jun 5, 2009 Application Note This application note explains configuration&#13;&#10;requirements to assist users to successfully program and set up this interface type. It also compares SGMII to other gigabit Ethernet standards and interfaces. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3869.pdf English documents 692438 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3869 Implementing SGMII Interfaces on the PowerQUICC™ III /secured/assets/documents/en/application-note/AN3869.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N Implementing SGMII Interfaces on the PowerQUICC™ III 692.4 KB AN3869 N 1244236817778728476903 /docs/en/application-note/AN3781.pdf 2010-05-11 1243968993550696784184 PSP 29 Jun 2, 2009 Application Note This application note explains the procedures to utilize the extra FC (Flow Control) credits for PCI Express inbound posted memory write transactions, which is currently a hidden feature for the Power QUICC III&#8482; devices. None /docs/en/application-note/AN3781.pdf English documents 476033 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3781.pdf Utilizing Extra FC Credits for PCI Express Inbound Posted Memory Write Transactions in PowerQUICC III&#8482; Devices /docs/en/application-note/AN3781.pdf documents 645036621402383989 Application Note N en None pdf 0 N Utilizing Extra FC Credits for PCI Express Inbound Posted Memory Write Transactions in PowerQUICC III&#8482; Devices 476.0 KB AN3781 N 1243968993550696784184 /docs/en/application-note/AN3661.pdf 2016-10-31 1231458979010730219558 PSP 30 Jan 8, 2009 Application Note The following application note details a procedure for programming and resetting MSC8156 or MSC8144 StarCore<sup>&#174;</sup> DSPs over a serial RapidIO interface from an external host. None /docs/en/application-note/AN3661.pdf English documents 655626 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3661.pdf RapidIO Technology in Wireless Base Stations: Programming DSPs over a RapidIO Interconnect /docs/en/application-note/AN3661.pdf documents 645036621402383989 Application Note N en None pdf 0 N N RapidIO Technology in Wireless Base Stations: Programming DSPs over a RapidIO Interconnect 655.6 KB AN3661 N 1231458979010730219558 /docs/en/application-note/AN3550.pdf 2016-10-31 1208458263255715391554 PSP 31 Oct 22, 2008 Application Note This application note describes an example of how to use an external DMA engine with a Serial RapidIO&#174; interface. None /docs/en/application-note/AN3550.pdf English documents 505720 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3550.pdf Using an External DMA Controller with Freescale Processors that Support Serial RapidIO® Technology /docs/en/application-note/AN3550.pdf documents 645036621402383989 Application Note N en None pdf 1.0 N Using an External DMA Controller with Freescale Processors that Support Serial RapidIO® Technology 505.7 KB AN3550 N 1208458263255715391554 /docs/en/application-note/AN3369.pdf 2007-04-09 1176147669904707686124 PSP 32 Sep 11, 2008 Application Note This document expands on the description of the double data rate (DDR2) memory controller programmable registers described in the reference manuals for PowerQUICC processors. The corresponding material in the reference manual defines the function of each field in the programmable registers. This application note focuses when and why to select certain configurations of the bits and fields in the DDR2 registers to achieve efficient DDR programming. None /docs/en/application-note/AN3369.pdf English documents 535277 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3369.pdf PowerQUICC<sup>&#174;</sup> DDR2 SDRAM Controller Register Setting Considerations /docs/en/application-note/AN3369.pdf documents 645036621402383989 Application Note N en None Y pdf 5.0 N PowerQUICC<sup>&#174;</sup> DDR2 SDRAM Controller Register Setting Considerations 535.3 KB AN3369 N 1176147669904707686124 /docs/en/application-note/AN3542.pdf 2016-10-31 1202329207598722883383 PSP 33 Jan 25, 2008 Application Note AN3542: This application note discusses the differences between SMP and AMP (asymmetric multi-processor) OSs, booting options and features of the MPC8572E, and configuration of shared and non-shared resources between cores. This application note also provides a description of the boot process implemented by Uboot and Linux that is provided as part of the MPC8572E development system board support package. None /docs/en/application-note/AN3542.pdf English documents 519909 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3542.pdf AN3542, SMP Boot Process for Dual E500 Cores - Application Notes /docs/en/application-note/AN3542.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN3542, SMP Boot Process for Dual E500 Cores - Application Notes 519.9 KB AN3542 N 1202329207598722883383 /docs/en/application-note/AN3544.pdf 2016-10-31 1198270786976715604383 PSP 34 Dec 21, 2007 Application Note This application note provides an overview and specific strategies for cache coherency and potential performance impacts in the PowerQUICC<sup>&#174;</sup> II Pro and PowerQUICC III families. It focuses on data coherency and potential system issues, as well as some concerns associated with having multiple DMA devices. It also discusses the specific steps and interdependencies required to implement hardware enforced cache coherency. None /docs/en/application-note/AN3544.pdf English documents 547694 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3544.pdf PowerQUICC™ Data Cache Coherency /docs/en/application-note/AN3544.pdf documents 645036621402383989 Application Note N en None pdf 0 N PowerQUICC™ Data Cache Coherency 547.7 KB AN3544 N 1198270786976715604383 /docs/en/application-note/AN3441.pdf 2016-10-31 1191253168152709402147 PSP 35 Dec 17, 2007 Application Note This document describes aspects of memory synchronization and cache coherency requirements for NXP&#8217;s PowerQUICC<sup>&#174;</sup>&#8482; III product family. Coherency and synchronization need be considered, both for data and instructions, when initializing memory or moving memory contents from one location to another. None /docs/en/application-note/AN3441.pdf English documents 188954 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3441.pdf Coherency and Synchronization Requirements for PowerQUICC™ III /docs/en/application-note/AN3441.pdf documents 645036621402383989 Application Note N en None pdf 1 N Coherency and Synchronization Requirements for PowerQUICC™ III 189.0 KB AN3441 N 1191253168152709402147 /docs/en/application-note/AN3537.pdf 2016-10-31 1196114880779719950774 PSP 36 Dec 6, 2007 Application Note The enhanced three-speed Ethernet controller (eTSEC) offered on many PowerQUICC&#8482; II Pro, PowerQUICC&#8482; III, and other devices, allows for flexible manipulation of incoming and outgoing Ethernet data. One such feature is the ability to receive and propagate padded, or &#8220;shimmed,&#8221; OSI layer 2 data to accommodate custom routing or direction of Ethernet data within a network. This application note describes what the shimming functionality does and the details of how to best utilize it. None /docs/en/application-note/AN3537.pdf English documents 497175 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3537.pdf Accommodating Layer 2 Padding (Shimming) with the Enhanced Three-Speed Ethernet Controller (eTSEC) /docs/en/application-note/AN3537.pdf documents 645036621402383989 Application Note N en None pdf 1 N Accommodating Layer 2 Padding (Shimming) with the Enhanced Three-Speed Ethernet Controller (eTSEC) 497.2 KB AN3537 N 1196114880779719950774 /docs/en/application-note/AN3532.pdf 2016-10-31 1196228463425717224884 PSP 37 Nov 27, 2007 Application Note This application note provides an introduction to the error correcting code (ECC) technology as well as an aid to initialization and error recovery on Our PowerQUICC<sup>&#174;</sup> III family of processors. None /docs/en/application-note/AN3532.pdf English documents 572952 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3532.pdf Error Correction and Error Handling on PowerQUICC (TM) III Processors /docs/en/application-note/AN3532.pdf documents 645036621402383989 Application Note N en None pdf 0 N Error Correction and Error Handling on PowerQUICC (TM) III Processors 573.0 KB AN3532 N 1196228463425717224884 /docs/en/application-note/AN3533.pdf 2007-11-08 1194558645992741221612 PSP 38 Nov 8, 2007 Application Note This application note explains how to program one of the eLBC&#8217;s user-programmable machines (UPMs) to control an SDRAM memory device. None /docs/en/application-note/AN3533.pdf English documents 574761 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3533.pdf Programming the User-Programmable Machine (UPM) for SDRAM Memory Devices /docs/en/application-note/AN3533.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N Programming the User-Programmable Machine (UPM) for SDRAM Memory Devices 574.8 KB AN3533 N 1194558645992741221612 /docs/en/application-note/AN3445.pdf 2016-10-31 1194389310604697206738 PSP 39 Oct 31, 2007 Application Note AN3445: This application note outlines general, high-level, architectural differences between the e300 and e500 family processors. The e300 family (which are based on the original 603 design) was designed to the original PowerPC architecture definition. The e500v1 and e500v2 processors are designed to what was originally the PowerPC Book E architecture and NXP?s embedded implementation standards (EIS). None /docs/en/application-note/AN3445.pdf English documents 934951 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3445.pdf AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3445.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes 935.0 KB AN3445 N 1194389310604697206738 /docs/en/application-note/AN3531.pdf 2016-10-31 1194389312415718217914 PSP 40 Oct 31, 2007 Application Note AN3531: This application note outlines general, high-level, architectural differences between the e600 and e500 family processors. Is intended as a general guideline for programmers and system designers who are assessing the efforts required in migrating to e500-based devices. None /docs/en/application-note/AN3531.pdf English documents 961596 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3531.pdf AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3531.pdf documents 645036621402383989 Application Note N en None pdf 0 N N AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes 961.6 KB AN3531 N 1194389312415718217914 /docs/en/application-note/AN2910.pdf 2016-10-31 1128961595061725581551 PSP 41 Mar 27, 2007 Application Note These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. None /docs/en/application-note/AN2910.pdf English documents 619650 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2910.pdf Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf documents 645036621402383989 Application Note N en None pdf 2 N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces 619.7 KB AN2910 N 1128961595061725581551 Application Note Software 3 /secured/assets/documents/en/application-note-software/AN3966SW.zip 2016-10-31 1258066894053701788655 PSP 44 Nov 10, 2009 Application Note Software Registration With Click-Thru Software Licensing Agreement /secured/assets/documents/en/application-note-software/AN3966SW.zip English documents 330857 1395958162559706127527 789425793691620447 2022-12-07 Y /webapp/Download?colCode=AN3966SW&appType=license Software to accompany application note AN3966 /secured/assets/documents/en/application-note-software/AN3966SW.zip documents 789425793691620447 Application Note Software N en Extended zip 0 Y N Software to accompany application note AN3966 330.9 KB AN3966SW N 1258066894053701788655 /docs/en/application-note-software/AN3661SW.zip 2009-01-09 1231523385210702386268 PSP 45 Jan 8, 2009 Application Note Software None /docs/en/application-note-software/AN3661SW.zip English documents 7354 None 789425793691620447 2022-12-07 /docs/en/application-note-software/AN3661SW.zip AN3661 Associated Software /docs/en/application-note-software/AN3661SW.zip documents 789425793691620447 Application Note Software N en None D zip 0 N AN3661 Associated Software 7.4 KB AN3661SW N 1231523385210702386268 /docs/en/application-note-software/AN3432.pdf 2007-07-28 1185652886394699344557 PSP 46 Jul 28, 2007 Application Note Software This application note looks at the use of the NXP regular expression pattern matching engine (PME) along with its stateful rules to enable content processing of SIP messages at gigabit rates. None /docs/en/application-note-software/AN3432.pdf English documents 160216 None 789425793691620447 2022-12-07 /docs/en/application-note-software/AN3432.pdf PowerQUICC<sup>&#174;</sup> SIP Firewall Traversal: Using NXP<sup>&#174;</sup> Stateful Rules /docs/en/application-note-software/AN3432.pdf documents 789425793691620447 Application Note Software N en None D pdf 0 N PowerQUICC<sup>&#174;</sup> SIP Firewall Traversal: Using NXP<sup>&#174;</sup> Stateful Rules 160.2 KB AN3432 N 1185652886394699344557 Data Sheet 1 /docs/en/data-sheet/MPC8572EEC.pdf 2008-07-11 1215805936357717798138 PSP 3 Mar 1, 2016 Data Sheet Data Sheet MPC8572EEC: This document describes the electrical characteristics of the MPC8572E PowerQUICC<sup>&#174;</sup> III integrated processor. None /docs/en/data-sheet/MPC8572EEC.pdf English 1147485 None Data Sheet 2022-12-07 N /docs/en/data-sheet/MPC8572EEC.pdf MPC8572E PowerQUICC<sup>&#174;</sup> III Integrated Processor Hardware Specifications /docs/en/data-sheet/MPC8572EEC.pdf documents 980000996212993340 Data Sheet N Y en None Y t520 pdf 7 N N MPC8572E PowerQUICC<sup>&#174;</sup> III Integrated Processor Hardware Specifications 1.1 MB MPC8572EEC N 1215805936357717798138 Fact Sheet 1 /docs/en/fact-sheet/MPC8572FS.pdf 2006-07-24 1153716175375698320991 PSP 1 Jan 31, 2008 Fact Sheet Fact Sheet The MPC8572E family of processors is designed to offer clock speeds from 1.067 GHz up to 1.5 GHz, combining two powerful processor cores, enhanced peripherals and high-speed interconnect technology to balance processor performance with I/O system throughput. Based on the scalable e500 system-on-chip (SoC) platform built on Power Architecture &#174; technology, they deliver dual-core gigahertz-plus communications processing performance. None /docs/en/fact-sheet/MPC8572FS.pdf English 258143 None Fact Sheet 2022-12-07 /docs/en/fact-sheet/MPC8572FS.pdf MPC8572E PowerQUICC<sup>&#174;</sup> &#174; III Processor - Fact Sheet /docs/en/fact-sheet/MPC8572FS.pdf documents 736675474163315314 Fact Sheet N Y en None Y t523 pdf 4 N MPC8572E PowerQUICC<sup>&#174;</sup> &#174; III Processor - Fact Sheet 258.1 KB MPC8572FS N 1153716175375698320991 Package Information 1 /docs/en/package-information/FC-PBGAPRES.pdf 2016-10-31 1273780789511716723050 PSP 47 Jul 8, 2015 Package Information This document is a presentation on understanding the FC-PBGA package. None /docs/en/package-information/FC-PBGAPRES.pdf English documents 5219387 None 302435339416912908 2022-12-07 N /docs/en/package-information/FC-PBGAPRES.pdf Flip Chip Plastic Ball Grid Array (FC-PBGA) Presentation /docs/en/package-information/FC-PBGAPRES.pdf documents 302435339416912908 Package Information N en None pdf 1 N N Flip Chip Plastic Ball Grid Array (FC-PBGA) Presentation 5.2 MB FC-PBGAPRES N 1273780789511716723050 Quick Reference Guide 1 /docs/en/quick-reference-guide/MPC8572ECFG.pdf 2008-02-04 1202161387706708958941 PSP 48 Oct 30, 2007 Quick Reference Guide None /docs/en/quick-reference-guide/MPC8572ECFG.pdf English documents 279698 None 803735842453594974 2022-12-07 /docs/en/quick-reference-guide/MPC8572ECFG.pdf MPC8572DS Development System Configuration Guide /docs/en/quick-reference-guide/MPC8572ECFG.pdf documents 803735842453594974 Quick Reference Guide N en None Y pdf 0 N MPC8572DS Development System Configuration Guide 279.7 KB MPC8572ECFG N 1202161387706708958941 Reference Manual 6 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 2016-10-31 1319210247754725815434 PSP 4 Jun 26, 2014 Reference Manual This reference manual describes the resources defined for the Power ISA embedded environment. Registration without Disclaimer /secured/assets/documents/en/reference-manual/EREF_RM.pdf English documents 10448185 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=EREF_RM EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /secured/assets/documents/en/reference-manual/EREF_RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 1 Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 10.4 MB EREF_RM N 1319210247754725815434 /docs/en/reference-manual/e500CORERMAD.pdf 2016-10-31 1152820363245707387417 PSP 5 Sep 11, 2012 Reference Manual E500CORER: This errata document describes corrections to the PowerPC &#8482; e500 Core Family Reference Manual, Revision 1. None /docs/en/reference-manual/e500CORERMAD.pdf English documents 117856 None 500633505221135046 2022-12-07 N /docs/en/reference-manual/e500CORERMAD.pdf E500CORER, Errata to PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/e500CORERMAD.pdf documents 500633505221135046 Reference Manual N en None pdf 1.2 N N E500CORER, Errata to PowerPC ™ e500 Core Family - Reference Manual 117.9 KB E500CORERMAD N 1152820363245707387417 /docs/en/reference-manual/MPC8572ERMAD.pdf 2008-05-21 1211408868437728056062 PSP 6 Oct 14, 2009 Reference Manual This document describes corrections to the MPC8572E PowerQUICC<sup>&#174;</sup>&#8482; III Integrated Host Processor Reference Manual, Revision 2. None /docs/en/reference-manual/MPC8572ERMAD.pdf English documents 563500 None 500633505221135046 2022-12-07 /docs/en/reference-manual/MPC8572ERMAD.pdf Errata to MPC8572E PowerQUICC<sup>&#174;</sup>&#8482; III Integrated Processor Reference Manual, Rev. 2 /docs/en/reference-manual/MPC8572ERMAD.pdf documents 500633505221135046 Reference Manual N en None N pdf 2.2 N Errata to MPC8572E PowerQUICC<sup>&#174;</sup>&#8482; III Integrated Processor Reference Manual, Rev. 2 563.5 KB MPC8572ERMAD N 1211408868437728056062 /secured/assets/documents/en/reference-manual/EMBMCRM.pdf 2016-10-31 1247173677125723218813 PSP 7 Jul 20, 2009 Reference Manual Multicore devices provide a path forward for increased performance. This path requires comprehensive and pervasive system and software changes as well as new, innovative hardware designs to ensure that the software can take advantage of the increased computational power. NXP Semiconductors, Inc. has years of experience with many types of embedded multicore devices and thus can ensure that all necessary components are present to ease the software burden and to avoid having an inefficient core. This bala Registration without Disclaimer /secured/assets/documents/en/reference-manual/EMBMCRM.pdf English documents 1486324 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=EMBMCRM Embedded Multicore: An Introduction /secured/assets/documents/en/reference-manual/EMBMCRM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 0 Y N Embedded Multicore: An Introduction 1.5 MB EMBMCRM N 1247173677125723218813 /docs/en/reference-manual/E500CORERM.pdf 2016-10-31 111qmdXB PSP 8 May 11, 2005 Reference Manual The primary objective of this user&#8217;s manual is to describe the functionality of the e500 embedded microprocessor core for software and hardware developers. The e500 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the PowerPC architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words in the 64-bit general-purpose registers (GPRs). None /docs/en/reference-manual/E500CORERM.pdf English documents 5707515 None 500633505221135046 2022-12-07 /docs/en/reference-manual/E500CORERM.pdf PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/E500CORERM.pdf documents 500633505221135046 Reference Manual N en None pdf 1 N PowerPC ™ e500 Core Family - Reference Manual 5.7 MB E500CORERM N 111qmdXB /docs/en/reference-manual/MPC8572ERM.pdf 2007-07-16 1184623419032690386458 PSP 2 May 23, 2008 Reference Manual Reference Manual This reference manual defines the functionality of the MPC8572E. This device integrates two PowerPC&#8482; processor cores, based on Power Architecture&#8482; technology, with system logic required for networking, telecommunications, and wireless infrastructure applications. None /docs/en/reference-manual/MPC8572ERM.pdf English 16160528 None Reference Manual 2025-03-08 /docs/en/reference-manual/MPC8572ERM.pdf MPC8572E Reference Manual /docs/en/reference-manual/MPC8572ERM.pdf documents 500633505221135046 Reference Manual N Y en None Y t877 pdf 2 N MPC8572E Reference Manual 16.2 MB MPC8572ERM N 1184623419032690386458 Supporting Information 2 /docs/en/supporting-information/FSLNISTCAVP.pdf 2016-11-09 1368836090577704535160 PSP 49 Oct 28, 2016 Supporting Information FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. None /docs/en/supporting-information/FSLNISTCAVP.pdf English documents 303546 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1.9 N N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 303.5 KB FSLNISTCAVP N 1368836090577704535160 /docs/en/supporting-information/MPC8572EFAMPECI.pdf 2016-10-31 1232680175270712682745 PSP 50 Dec 10, 2010 Supporting Information Customer Export Control Information Document None /docs/en/supporting-information/MPC8572EFAMPECI.pdf English documents 21417 None 371282830530968666 2023-06-19 N /docs/en/supporting-information/MPC8572EFAMPECI.pdf MPC8572E Family Customer Export Control Information /docs/en/supporting-information/MPC8572EFAMPECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1 N N MPC8572E Family Customer Export Control Information 21.4 KB MPC8572EFAMPECI N 1232680175270712682745 User Guide 2 /docs/en/user-guide/MPC8572DSUG.pdf 2008-04-22 1208892472886723833004 PSP 42 Jan 12, 2009 User Guide MPC8572DS is a high-performance computing, evaluation and development platform supporting the MPC8572 processor built on Power Architecture technology. None /docs/en/user-guide/MPC8572DSUG.pdf English documents 1114979 None 132339537837198660 2023-06-18 /docs/en/user-guide/MPC8572DSUG.pdf MPC8572 Development System User&#8217;s Guide /docs/en/user-guide/MPC8572DSUG.pdf documents 132339537837198660 User Guide N en None Y pdf 1 N MPC8572 Development System User&#8217;s Guide 1.1 MB MPC8572DSUG N 1208892472886723833004 /docs/en/user-guide/MPC8572DSBE.pdf 2008-05-16 1210970430129731816114 PSP 43 Apr 11, 2008 User Guide This document describes the known errata and limitations of the Whitefin Development System. In all cases, if an errata has a work-around, it is applied to the system before shipped to customers. None /docs/en/user-guide/MPC8572DSBE.pdf English documents 486061 None 132339537837198660 2023-06-18 /docs/en/user-guide/MPC8572DSBE.pdf MPC8572DS (Whitefin) Development System Errata /docs/en/user-guide/MPC8572DSBE.pdf documents 132339537837198660 User Guide N en None Y pdf 2.1 N MPC8572DS (Whitefin) Development System Errata 486.1 KB MPC8572DSBE N 1210970430129731816114 White Paper 9 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf 2016-10-31 1227561595497709456436 PSP 51 Aug 15, 2008 White Paper Network security protocols and applications use a variety of cryptographic algorithms to achieve these high-level goals. Because cryptography is computationally intensive, hardware acceleration is highly desirable when cryptographic algorithms are frequent system functions. Registration without Disclaimer /secured/assets/documents/en/white-paper/CRYPTOWP.pdf English documents 580121 None 918633085541740938 2022-12-07 Y /webapp/Download?colCode=CRYPTOWP Understanding Cryptographic Performance /secured/assets/documents/en/white-paper/CRYPTOWP.pdf documents 918633085541740938 White Paper N en Extended Y pdf 3 Y N Understanding Cryptographic Performance 580.1 KB CRYPTOWP N 1227561595497709456436 /docs/en/white-paper/DDRSDRAMWP.pdf 2016-10-31 1208376896761708228520 PSP 52 Apr 16, 2008 White Paper The focus of this white paper is to provide the end user with high level design considerations and/or trade-offs associated with migrating from SDRAM to DDR SDRAM-based designs. None /docs/en/white-paper/DDRSDRAMWP.pdf English documents 735286 None 918633085541740938 2023-06-19 N /docs/en/white-paper/DDRSDRAMWP.pdf Comparison of DDRx and SDRAM /docs/en/white-paper/DDRSDRAMWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N N Comparison of DDRx and SDRAM 735.3 KB DDRSDRAMWP N 1208376896761708228520 /docs/en/white-paper/MULTICOREFTFWP.pdf 2007-06-21 1182464945682712255909 PSP 53 Jan 31, 2008 White Paper NXP&#8217;s next-generation Multi-core Communications Platform is an innovative evolution of our established&#13;&#10;PowerQUICC<sup>&#174;</sup> architecture designed to enable a new era of networking where the reliability, security and quality of&#13;&#10;service for every connection matters. This white paper introduces you to the technical architecture of this platform&#13;&#10;and its comprehensive approach to solving the programmability problem. None /docs/en/white-paper/MULTICOREFTFWP.pdf English documents 317969 None 918633085541740938 2023-06-19 /docs/en/white-paper/MULTICOREFTFWP.pdf A Smarter Approach to Multi-Core: NXP&#8217;s Next-Generation Communications Platform /docs/en/white-paper/MULTICOREFTFWP.pdf documents 918633085541740938 White Paper N en None Y pdf 1 N A Smarter Approach to Multi-Core: NXP&#8217;s Next-Generation Communications Platform 318.0 KB MULTICOREFTFWP N 1182464945682712255909 /docs/en/white-paper/MPC8572EWP.pdf 2007-02-01 1170362096385722242536 PSP 54 Jun 15, 2007 White Paper In this white paper, we will use the term "application-aware networking" to refer to the function of network nodes processing application layer protocol and content &#8211; in addition to packet header &#8211; in order to perform the networking features they are designed to provide. This white paper describes how high-performance, cost-effective application-aware networking equipment can be designed with the MPC8572E. None /docs/en/white-paper/MPC8572EWP.pdf English documents 845007 None 918633085541740938 2023-06-19 /docs/en/white-paper/MPC8572EWP.pdf Designing Application-Aware Networking Equipment with the PowerQUICC<sup>&#174;</sup> III MPC8572E /docs/en/white-paper/MPC8572EWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N Designing Application-Aware Networking Equipment with the PowerQUICC<sup>&#174;</sup> III MPC8572E 845.0 KB MPC8572EWP N 1170362096385722242536 /docs/en/white-paper/PQMPC8572EWP.pdf 2007-06-19 1182279281048723030722 PSP 55 Jun 15, 2007 White Paper None /docs/en/white-paper/PQMPC8572EWP.pdf English documents 301430 None 918633085541740938 2023-06-19 /docs/en/white-paper/PQMPC8572EWP.pdf Designing IDS/IPS with the PowerQUICC<sup>&#174;</sup>&#174; III MPC8572E /docs/en/white-paper/PQMPC8572EWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N Designing IDS/IPS with the PowerQUICC<sup>&#174;</sup>&#174; III MPC8572E 301.4 KB PQMPC8572EWP N 1182279281048723030722 /docs/en/white-paper/UTMMPC8572EWP.pdf 2007-06-19 1182279283464714008667 PSP 56 Jun 15, 2007 White Paper None /docs/en/white-paper/UTMMPC8572EWP.pdf English documents 361209 None 918633085541740938 2023-06-19 /docs/en/white-paper/UTMMPC8572EWP.pdf Designing UTM with the PowerQUICC<sup>&#174;</sup>&#174; III MPC8572E /docs/en/white-paper/UTMMPC8572EWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N Designing UTM with the PowerQUICC<sup>&#174;</sup>&#174; III MPC8572E 361.2 KB UTMMPC8572EWP N 1182279283464714008667 /docs/en/white-paper/FIREWALLVPNWP.pdf 2007-02-01 1170362082872730223398 PSP 57 Jun 15, 2007 White Paper The stateful inspection firewall/IPSec VPN security gateway has been&#8212;and still is&#8212;the most critical piece of network security equipment for most enterprises. Firewall/VPN is a perimeter-defense device, typically deployed where the enterprise&#8217;s internal network meets the open Internet. This white paper focuses on describing how the MPC8572E can be used for firewall/VPN design. None /docs/en/white-paper/FIREWALLVPNWP.pdf English documents 888797 None 918633085541740938 2022-12-07 /docs/en/white-paper/FIREWALLVPNWP.pdf Designing Firewall/VPN with the PowerQUICC<sup>&#174;</sup> III MPC8572E /docs/en/white-paper/FIREWALLVPNWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N Designing Firewall/VPN with the PowerQUICC<sup>&#174;</sup> III MPC8572E 888.8 KB FIREWALLVPNWP N 1170362082872730223398 /docs/en/white-paper/KASPERSKYWP.pdf 2007-02-01 1170362100151719945730 PSP 58 Jun 15, 2007 White Paper Accelerated Anti-Virus (Accelerated AV) is a high-performance network anti-virus solution platform jointly offered by Kaspersky Lab (Kaspersky) and NXP Semiconductors, Inc. (NXP) to OEM vendors. Accelerated AV is based on NXP&#8217;s MPC8572E PowerQUICC<sup>&#174;</sup> III processor and Kaspersky&#8217;s SafeStream signatures database. None /docs/en/white-paper/KASPERSKYWP.pdf English documents 637783 None 918633085541740938 2023-06-19 /docs/en/white-paper/KASPERSKYWP.pdf NXP<sup>&#174;</sup>-Kaspersky Accelerated Antivirus Solution Platform for OEM Vendors /docs/en/white-paper/KASPERSKYWP.pdf documents 918633085541740938 White Paper N en None Y pdf 1 N NXP<sup>&#174;</sup>-Kaspersky Accelerated Antivirus Solution Platform for OEM Vendors 637.8 KB KASPERSKYWP N 1170362100151719945730 /docs/en/white-paper/multicoreWP.pdf 2005-01-25 1106677389248718091991 PSP 59 Jan 25, 2005 White Paper white paper None /docs/en/white-paper/multicoreWP.pdf English documents 115647 None 918633085541740938 2023-06-19 /docs/en/white-paper/multicoreWP.pdf Multi-Core Microprocessors in Embedded Applications /docs/en/white-paper/multicoreWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N Multi-Core Microprocessors in Embedded Applications 115.6 KB MULTICOREWP N 1106677389248718091991 true Y Products

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