Layerscape 2084A and 2044A | NXP Semiconductors

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Layerscape 2084A and 2044A Multicore Processors

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The LS2 family of processors delivers unprecedented performance and integration for tomorrow's smarter, more capable networks. The eight-core LS2084A and the four-core LS2044A multicore processors offer Arm® Cortex®- A72 cores with the advanced, high-performance datapath and network peripheral interfaces required for networking, telecom/datacom, wireless infrastructure, military, aerospace and automotive applications.

The next-generation datapath architecture, combined with a powerful software toolkit, provides a higher level of hardware abstraction and makes software development quick and simple.

This combination balances ease-of-use with high-performance processing in a Linux® environment that is familiar to any software programmer. Customers can fully exploit the underlying hardware and easily adapt to network changes for real-time 'soft' control over the network.

Layerscape processors are part of NXP's EdgeVerse™ edge computing platform.

Block Diagram

LS2084A Processor Block Diagram

LS2084A Processor Block Diagram
Get diagram PDF

Features

Core Complex

  • Eight 64-bit Arm Cortex-A72 CPUs
    • Up to 2 GHz,
    • Clusters of two cores sharing 1 MB L2 cache
  • 1 MB L3 platform cache
  • Two 64-bit DDR4 SDRAM memory controllers
    • ECC and interleaving support,
    • Up to 2.1 GT/s

Networking Elements

  • Wire Rate I/O processor, featuring:
    • 8x 10 GbE
    • 8x 1 GbE
    • L2 switching on the Ethernet interface
    • XAUI/XFI/KR and SGMII
    • MACSec on up to four 1/10 GbE
  • 2x SATA 3.0
  • 4x PCIe Gen 3 controllers
  • SR-IOV support, Root Complex

Accelerators and Memory Control

  • 20 Gb/s SEC crypto acceleration
  • 10 Gb/s Pattern Matching Engine
  • 20 Gb/s Data Compression Engine
  • 4 PCIe controllers (Gen3) supporting 1x8, 4x4, 4x2, 4x1 lane configurations

Basic Peripherals and Interconnect

  • Support for hardware virtualization and partitioning enforcement
  • Implements trust architecture combined with TrustZone®
    • Service processor (SP) provides pre-boot initialization and secure-boot capabilities
  • 2x USB 3.0 with PHY
  • Enhanced secure digital host controller
  • Serial peripheral interface (SPI) controller
  • Quad Serial peripheral interface (QSPI) controller
  • Four I²C controllers
  • Two DUARTs
  • Integrated flash controller (IFC 2.0) supporting NAND and NOR flash

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N true 0 PSPLS2084Aen 23 Application Note Application Note t789 15 Data Sheet Data Sheet t520 1 Errata Errata t522 1 Fact Sheet Fact Sheet t523 1 Reference Manual Reference Manual t877 2 Supporting Information Supporting Information t531 1 User Manual User Manual t1009 1 White Paper White Paper t530 1 en_US en_US en Data Sheet Data Sheet 1 1 4 English The LS2084A and LS2044A have eight and four, respectively, Arm® Cortex®-A72 cores built on Armv8-A architecture with high-performance data path acceleration and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and military/aerospace applications. 1522659119179715436323 PSP 1.7 MB Registration without Disclaimer None documents Extended 1522659119179715436323 /secured/assets/documents/en/data-sheet/LS2084A.pdf 1655840 /secured/assets/documents/en/data-sheet/LS2084A.pdf LS2084A documents Y N 2018-04-02 LS2084A/LS2044A Data Sheet /webapp/Download?colCode=LS2084A /secured/assets/documents/en/data-sheet/LS2084A.pdf Data Sheet N 980000996212993340 2022-12-07 pdf Y en Jun 15, 2021 980000996212993340 Data Sheet Y N LS2084A/LS2044A Data Sheet Reference Manual Reference Manual 2 2 1 English The LS2088A, LS2044A, LS2084A, LS2048A can be used for control and dataplane, data path, and advanced IO processing in routers, switches, gateways, and general-purpose embedded computing systems. Like other QorIQ products, the LS2088A’s high level of integration offers significant space, weight, and power benefits compared to multiple discrete devices. 1523543520051699158347 PSP 57.6 MB Registration without Disclaimer None documents Extended 1523543520051699158347 /secured/assets/documents/en/reference-manual/LS2088A_LS2084A_LS2048A_LS2044ARM.pdf 57609863 /secured/assets/documents/en/reference-manual/LS2088A_LS2084A_LS2048A_LS2044ARM.pdf LS2088ARM documents Y N 2018-04-12 QorIQ LS2088A Reference Manual /webapp/Download?colCode=LS2088ARM /secured/assets/documents/en/reference-manual/LS2088A_LS2084A_LS2048A_LS2044ARM.pdf Reference Manual N 500633505221135046 2023-06-18 pdf Y en Sep 28, 2020 500633505221135046 Reference Manual Y N QorIQ LS2088A Reference Manual 3 0 English LS2088ASECRM: This manual documents the LS2088A's security engine, the cryptographic acceleration and offloading hardware. 1525684676209714011650 PSP 7.2 MB None None documents None 1525684676209714011650 /docs/en/reference-manual/LS2088ASECRM.pdf 7191599 /docs/en/reference-manual/LS2088ASECRM.pdf LS2088ASECRM documents N N 2018-05-07 LS2088ASECRM, LS2088A Security (SEC) Reference Manual - Reference Manual /docs/en/reference-manual/LS2088ASECRM.pdf /docs/en/reference-manual/LS2088ASECRM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf N en May 7, 2018 500633505221135046 Reference Manual Y N LS2088ASECRM, LS2088A Security (SEC) Reference Manual - Reference Manual Application Note Application Note 15 4 3 English AN5097: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR4 memory subsystem. 1428008859060729157318 PSP 1.1 MB Registration without Disclaimer None documents Extended 1428008859060729157318 /secured/assets/documents/en/application-note/AN5097.pdf 1120906 /secured/assets/documents/en/application-note/AN5097.pdf AN5097 documents Y N 2016-10-31 Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces /webapp/Download?colCode=AN5097 /secured/assets/documents/en/application-note/AN5097.pdf Application Note N 645036621402383989 2024-12-18 pdf Y en Jul 28, 2023 645036621402383989 Application Note Y N Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces 5 1 English AN12750: This application note describes 10GBase-KR link training to get optimal training parameters and the procedure to validate it. 1591185804970704148974 PSP 6.1 MB Registration without Disclaimer None documents Extended 1591185804970704148974 /secured/assets/documents/en/application-note/AN12750.pdf 6058065 /secured/assets/documents/en/application-note/AN12750.pdf AN12750 documents Y N 2020-06-03 Enabling 10GBase-KR on QorIQ Platforms Application Note /webapp/Download?colCode=AN12750 /secured/assets/documents/en/application-note/AN12750.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jul 29, 2022 645036621402383989 Application Note Y N Enabling 10GBase-KR on QorIQ Platforms Application Note 6 0 Chinese 1649067147403724850019zh PSP 155.1 KB None None documents None 1649067147403724850019 /docs/zh/application-note/AN13608.pdf 155124 /docs/zh/application-note/AN13608.pdf AN13608 documents N N 2022-04-04 Chaining FlexTimers on Layerscape Devices /docs/zh/application-note/AN13608.pdf /docs/zh/application-note/AN13608.pdf Application Note N 645036621402383989 2023-09-14 zh Apr 4, 2022 645036621402383989 Application Note Y N 将Layerscape器件上的FlexTimer串接起来 0 English 1649067147403724850019 PSP 155.1 KB None None documents None 1649067147403724850019 /docs/en/application-note/AN13608.pdf 155124 /docs/en/application-note/AN13608.pdf AN13608 documents N N 2022-04-04 Chaining FlexTimers on Layerscape Devices /docs/en/application-note/AN13608.pdf /docs/en/application-note/AN13608.pdf Application Note N 645036621402383989 2023-09-14 pdf N en Apr 4, 2022 645036621402383989 Application Note Y N Chaining FlexTimers on Layerscape Devices 7 4 English AN12572: This document describes how to enable backplane support for Layerscape and QorIQ devices with embedded support for this type of connection. 1567589575242748292636 PSP 194.6 KB None None documents None 1567589575242748292636 /docs/en/application-note/AN12572.pdf 194553 /docs/en/application-note/AN12572.pdf AN12572 documents N N 2019-09-04 Ethernet Backplane Driver Support Application Note /docs/en/application-note/AN12572.pdf /docs/en/application-note/AN12572.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 26, 2021 645036621402383989 Application Note Y N Ethernet Backplane Driver Support Application Note 8 0 English 1631544294418735262217 PSP 960.7 KB None None documents None 1631544294418735262217 /docs/en/application-note/AN13329.pdf 960672 /docs/en/application-note/AN13329.pdf AN13329 documents N N 2021-09-13 Network subsystem troubleshooting on DPAA2 devices (illustrated with LX2160) /docs/en/application-note/AN13329.pdf /docs/en/application-note/AN13329.pdf Application Note N 645036621402383989 2024-12-13 pdf N en Sep 13, 2021 645036621402383989 Application Note Y N Network subsystem troubleshooting on DPAA2 devices (illustrated with LX2160) 9 3 English AN4977: This document provides recommendations for new designs based on LS2088A family. 1526663500562728612399 PSP 792.7 KB Registration without Disclaimer None documents Extended 1526663500562728612399 /secured/assets/documents/en/application-note/AN4977.pdf 792711 /secured/assets/documents/en/application-note/AN4977.pdf AN4977 documents Y N 2018-05-18 QorIQ LS2088A Family Design Checklist /webapp/Download?colCode=AN4977 /secured/assets/documents/en/application-note/AN4977.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Feb 3, 2021 645036621402383989 Application Note Y N QorIQ LS2088A Family Design Checklist 10 0 Chinese AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ<sup>&#174;</sup> platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105zh PSP 1.0 MB None None documents None 1456317293250700197105 /docs/zh/application-note/AN5260.pdf 1027928 /docs/zh/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/zh/application-note/AN5260.pdf /docs/zh/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 zh Feb 24, 2016 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 1 English AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105 PSP 1.0 MB None None documents None 1456317293250700197105 /docs/en/application-note/AN5260.pdf 1027928 /docs/en/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf /docs/en/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 30, 2020 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 11 0 English AN12628: This application note explains how to optimize memory copy routines. 1573117464705697840062 PSP 485.1 KB None None documents None 1573117464705697840062 /docs/en/application-note/AN12628.pdf 485139 /docs/en/application-note/AN12628.pdf AN12628 documents N N 2019-11-07 Optimizing Memory Copy Routines Application Note /docs/en/application-note/AN12628.pdf /docs/en/application-note/AN12628.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 6, 2019 645036621402383989 Application Note Y N Optimizing Memory Copy Routines Application Note 12 1 English Solder joint and package temperature for Pb-free BGA in SnPB and Pb-free solders in IR or convection reflow ovens are discussed in this document. 1154542630989715908212 PSP 281.6 KB None None documents None 1154542630989715908212 /docs/en/application-note/AN3300.pdf 281637 /docs/en/application-note/AN3300.pdf AN3300 documents N N 2017-08-17 General soldering Temperature Process Guidelines /docs/en/application-note/AN3300.pdf /docs/en/application-note/AN3300.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Aug 16, 2017 645036621402383989 Application Note Y N General soldering Temperature Process Guidelines 13 0 English This application note presents configuration and example use cases of L2 switch (DPSW) and Edge Virtual Bridge (DPDMUX). 1500359342664720853564 PSP 650.1 KB Registration without Disclaimer None documents Extended 1500359342664720853564 /secured/assets/documents/en/application-note/AN11979.pdf 650083 /secured/assets/documents/en/application-note/AN11979.pdf AN11979 documents Y N 2017-07-17 AN11979, DPAA2 Ethernet Switch and Edge Virtual Bridge - Application Note /webapp/Download?colCode=AN11979 /secured/assets/documents/en/application-note/AN11979.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jul 18, 2017 645036621402383989 Application Note Y N AN11979, DPAA2 Ethernet Switch and Edge Virtual Bridge - Application Note 14 0 English AN5199: This document targets customers familiar with DPAA1 who would like to know more about DPAA2 before migrating to DPAA2 enabled devices. 1450813697769731607959 PSP 922.3 KB Registration without Disclaimer None documents Extended 1450813697769731607959 /secured/assets/documents/en/application-note/AN5199.pdf 922254 /secured/assets/documents/en/application-note/AN5199.pdf AN5199 documents Y N 2016-10-31 AN5199, Key Concepts for the Transition from DPAA1 to DPAA2 - Application Note /webapp/Download?colCode=AN5199 /secured/assets/documents/en/application-note/AN5199.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Dec 22, 2015 645036621402383989 Application Note Y N AN5199, Key Concepts for the Transition from DPAA1 to DPAA2 - Application Note 15 0 English AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. 1441302193437732651194 PSP 566.4 KB None None documents None 1441302193437732651194 /docs/en/application-note/AN5125.pdf 566365 /docs/en/application-note/AN5125.pdf AN5125 documents N N 2016-10-31 AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf /docs/en/application-note/AN5125.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Sep 3, 2015 645036621402383989 Application Note Y N AN5125, Introduction to Device Trees - Application Note 16 Rev. 0 English This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. 1305312143395731535528 PSP 577.2 KB Registration without Disclaimer None documents Extended 1305312143395731535528 /secured/assets/documents/en/application-note/AN4311.pdf 577164 /secured/assets/documents/en/application-note/AN4311.pdf AN4311 documents Y N 2016-10-31 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /webapp/Download?colCode=AN4311 /secured/assets/documents/en/application-note/AN4311.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 13, 2011 645036621402383989 Application Note Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 17 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939 /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors 18 0 English This document demonstrates how to determine the package temperature and thermal mass dependent moisture sensitivity level (MSL) of products to ensure reliable processing of moisture sensitive surface mount components. Comply with these recommendations to maintain package integrity of components during any heat exposure of board soldering and de-soldering. 1154542628855726115465 PSP 151.6 KB None None documents None 1154542628855726115465 /docs/en/application-note/AN3298.pdf 151612 /docs/en/application-note/AN3298.pdf AN3298 documents N N 2016-10-31 Solder Joint Temperature and Package Peak Temperature /docs/en/application-note/AN3298.pdf /docs/en/application-note/AN3298.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Aug 2, 2006 645036621402383989 Application Note Y N Solder Joint Temperature and Package Peak Temperature User Manual User Manual 1 19 53 English DPAA2 is a hardware-level networking architecture found on some NXP SoCs. This document provides technical information on this architecture mainly for software developers. 1582785451078700466276 PSP 6.0 MB Registration without Disclaimer None documents Extended 1582785451078700466276 /secured/assets/documents/en/user-guide/DPAA2UM.pdf 5987656 /secured/assets/documents/en/user-guide/DPAA2UM.pdf DPAA2UM documents Y N 2020-02-26 DPAA2 User Manual /webapp/Download?colCode=DPAA2UM /secured/assets/documents/en/user-guide/DPAA2UM.pdf User Manual N 309919593431037931 2023-09-21 pdf Y en Sep 19, 2023 309919593431037931 User Manual Y N DPAA2 User Manual Errata Errata 1 20 kb 2 English The current errata for LS2084/44A, released Feb 2023, Rev 2. It is an NDA document. Please see the Sharepoint site https://nxp1.sharepoint.com/teams/cext73/SitePages/Home.aspx (NDA and NXP-issued invite required), or contact your NXP representative. 1645462520310720216311 PSP None None documents None 1645462520310720216311 https://nxp1.sharepoint.com/teams/cext73/SitePages/Home.aspx https://nxp1.sharepoint.com/teams/cext73/SitePages/Home.aspx LX2084-ERRATA-LINK documents N N N 2022-02-21 LX2084 Errata https://nxp1.sharepoint.com/teams/cext73/SitePages/Home.aspx https://nxp1.sharepoint.com/teams/cext73/SitePages/Home.aspx Y Errata N 155452329886410597 Y 2023-05-23 URL en May 22, 2023 155452329886410597 Errata Y N https://nxp1.sharepoint.com/teams/cext73/SitePages/Home.aspx LX2084 Errata URL Fact Sheet Fact Sheet 1 21 0 English The Layerscape LS2044A and LS2084A multicore processors combine four and eight Arm® Cortex®-A72 cores, respectively, with the advanced, high-performance datapath and network peripheral interfaces required for networking, telecom/datacom, wireless infrastructure, military and aerospace applications. 1597863003792722925627 PSP 4.5 MB None None documents None 1597863003792722925627 /docs/en/fact-sheet/LS2084AFS.pdf 4512215 /docs/en/fact-sheet/LS2084AFS.pdf LS2084AFS documents N N 2020-08-19 LAYERSCAPE LS2044A AND LS2084A COMMUNICATIONS PROCESSORS /docs/en/fact-sheet/LS2084AFS.pdf /docs/en/fact-sheet/LS2084AFS.pdf Fact Sheet N 736675474163315314 2022-12-07 pdf N en Aug 19, 2020 736675474163315314 Fact Sheet Y N LAYERSCAPE LS2044A AND LS2084A COMMUNICATIONS PROCESSORS Supporting Information Supporting Information 1 22 1.9 English FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. 1368836090577704535160 PSP 303.5 KB None None documents None 1368836090577704535160 /docs/en/supporting-information/FSLNISTCAVP.pdf 303546 /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP documents N N 2016-11-09 FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf /docs/en/supporting-information/FSLNISTCAVP.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 28, 2016 371282830530968666 Supporting Information Y N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper White Paper White Paper 1 23 0 English Traditional WAN services that use enterprise routers and other networking equipment face new competition: managed services with software-defined WAN (SD-WAN) technology and traditional WAN services with network-function virtualization (NFV). 1536959379286712399360 PSP 138.0 KB None None documents None 1536959379286712399360 /docs/en/white-paper/VIRTUAL-SOFTWARE-SOLUTIONS-WP.pdf 138002 /docs/en/white-paper/VIRTUAL-SOFTWARE-SOLUTIONS-WP.pdf VIRTUAL-SOFTWARE-SOLUTIONS-WP documents N N 2018-09-14 VIRTUAL AND SOFTWARE SOLUTIONS: THE BATTLE FOR ENTERPRISE NETWORK SUPREMACY /docs/en/white-paper/VIRTUAL-SOFTWARE-SOLUTIONS-WP.pdf /docs/en/white-paper/VIRTUAL-SOFTWARE-SOLUTIONS-WP.pdf White Paper N 918633085541740938 2022-12-07 pdf N en Sep 14, 2018 918633085541740938 White Paper Y N VIRTUAL AND SOFTWARE SOLUTIONS: THE BATTLE FOR ENTERPRISE NETWORK SUPREMACY false 0 LS2084A downloads en true 1 Y PSP Y Y Application Note 15 /secured/assets/documents/en/application-note/AN5097.pdf 2016-10-31 1428008859060729157318 PSP 4 Jul 28, 2023 Application Note AN5097: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR4 memory subsystem. Registration without Disclaimer /secured/assets/documents/en/application-note/AN5097.pdf English documents 1120906 None 645036621402383989 2024-12-18 Y /webapp/Download?colCode=AN5097 Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces /secured/assets/documents/en/application-note/AN5097.pdf documents 645036621402383989 Application Note N en Extended Y pdf 3 Y N Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces 1.1 MB AN5097 N 1428008859060729157318 /secured/assets/documents/en/application-note/AN12750.pdf 2020-06-03 1591185804970704148974 PSP 5 Jul 29, 2022 Application Note AN12750: This application note describes 10GBase-KR link training to get optimal training parameters and the procedure to validate it. Registration without Disclaimer /secured/assets/documents/en/application-note/AN12750.pdf English documents 6058065 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN12750 Enabling 10GBase-KR on QorIQ Platforms Application Note /secured/assets/documents/en/application-note/AN12750.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N Enabling 10GBase-KR on QorIQ Platforms Application Note 6.1 MB AN12750 N 1591185804970704148974 /docs/en/application-note/AN13608.pdf 2022-04-04 1649067147403724850019 PSP 6 Apr 4, 2022 Application Note None /docs/en/application-note/AN13608.pdf English documents 155124 None 645036621402383989 2023-09-14 N /docs/en/application-note/AN13608.pdf Chaining FlexTimers on Layerscape Devices /docs/en/application-note/AN13608.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Chaining FlexTimers on Layerscape Devices 155.1 KB AN13608 N 1649067147403724850019 /docs/en/application-note/AN12572.pdf 2019-09-04 1567589575242748292636 PSP 7 Nov 26, 2021 Application Note AN12572: This document describes how to enable backplane support for Layerscape and QorIQ devices with embedded support for this type of connection. None /docs/en/application-note/AN12572.pdf English documents 194553 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN12572.pdf Ethernet Backplane Driver Support Application Note /docs/en/application-note/AN12572.pdf documents 645036621402383989 Application Note N en None Y pdf 4 N N Ethernet Backplane Driver Support Application Note 194.6 KB AN12572 N 1567589575242748292636 /docs/en/application-note/AN13329.pdf 2021-09-13 1631544294418735262217 PSP 8 Sep 13, 2021 Application Note None /docs/en/application-note/AN13329.pdf English documents 960672 None 645036621402383989 2024-12-13 N /docs/en/application-note/AN13329.pdf Network subsystem troubleshooting on DPAA2 devices (illustrated with LX2160) /docs/en/application-note/AN13329.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Network subsystem troubleshooting on DPAA2 devices (illustrated with LX2160) 960.7 KB AN13329 N 1631544294418735262217 /secured/assets/documents/en/application-note/AN4977.pdf 2018-05-18 1526663500562728612399 PSP 9 Feb 3, 2021 Application Note AN4977: This document provides recommendations for new designs based on LS2088A family. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4977.pdf English documents 792711 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4977 QorIQ LS2088A Family Design Checklist /secured/assets/documents/en/application-note/AN4977.pdf documents 645036621402383989 Application Note N en Extended Y pdf 3 Y N QorIQ LS2088A Family Design Checklist 792.7 KB AN4977 N 1526663500562728612399 /docs/en/application-note/AN5260.pdf 2016-10-31 1456317293250700197105 PSP 10 Nov 30, 2020 Application Note AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). None /docs/en/application-note/AN5260.pdf English documents 1027928 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5260.pdf PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N PBL Configuration using QCVS Application Note 1.0 MB AN5260 N 1456317293250700197105 /docs/en/application-note/AN12628.pdf 2019-11-07 1573117464705697840062 PSP 11 Nov 6, 2019 Application Note AN12628: This application note explains how to optimize memory copy routines. None /docs/en/application-note/AN12628.pdf English documents 485139 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN12628.pdf Optimizing Memory Copy Routines Application Note /docs/en/application-note/AN12628.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Optimizing Memory Copy Routines Application Note 485.1 KB AN12628 N 1573117464705697840062 /docs/en/application-note/AN3300.pdf 2017-08-17 1154542630989715908212 PSP 12 Aug 16, 2017 Application Note Solder joint and package temperature for Pb-free BGA in SnPB and Pb-free solders in IR or convection reflow ovens are discussed in this document. None /docs/en/application-note/AN3300.pdf English documents 281637 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3300.pdf General soldering Temperature Process Guidelines /docs/en/application-note/AN3300.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N General soldering Temperature Process Guidelines 281.6 KB AN3300 N 1154542630989715908212 /secured/assets/documents/en/application-note/AN11979.pdf 2017-07-17 1500359342664720853564 PSP 13 Jul 18, 2017 Application Note This application note presents configuration and example use cases of L2 switch (DPSW) and Edge Virtual Bridge (DPDMUX). Registration without Disclaimer /secured/assets/documents/en/application-note/AN11979.pdf English documents 650083 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN11979 AN11979, DPAA2 Ethernet Switch and Edge Virtual Bridge - Application Note /secured/assets/documents/en/application-note/AN11979.pdf documents 645036621402383989 Application Note N en Extended Y pdf 0 Y N AN11979, DPAA2 Ethernet Switch and Edge Virtual Bridge - Application Note 650.1 KB AN11979 N 1500359342664720853564 /secured/assets/documents/en/application-note/AN5199.pdf 2016-10-31 1450813697769731607959 PSP 14 Dec 22, 2015 Application Note AN5199: This document targets customers familiar with DPAA1 who would like to know more about DPAA2 before migrating to DPAA2 enabled devices. Registration without Disclaimer /secured/assets/documents/en/application-note/AN5199.pdf English documents 922254 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN5199 AN5199, Key Concepts for the Transition from DPAA1 to DPAA2 - Application Note /secured/assets/documents/en/application-note/AN5199.pdf documents 645036621402383989 Application Note N en Extended Y pdf 0 Y N AN5199, Key Concepts for the Transition from DPAA1 to DPAA2 - Application Note 922.3 KB AN5199 N 1450813697769731607959 /docs/en/application-note/AN5125.pdf 2016-10-31 1441302193437732651194 PSP 15 Sep 3, 2015 Application Note AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. None /docs/en/application-note/AN5125.pdf English documents 566365 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5125.pdf AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N AN5125, Introduction to Device Trees - Application Note 566.4 KB AN5125 N 1441302193437732651194 /secured/assets/documents/en/application-note/AN4311.pdf 2016-10-31 1305312143395731535528 PSP 16 May 13, 2011 Application Note This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4311.pdf English documents 577164 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4311 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /secured/assets/documents/en/application-note/AN4311.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev. 0 Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 577.2 KB AN4311 N 1305312143395731535528 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 17 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939 DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 /docs/en/application-note/AN3298.pdf 2016-10-31 1154542628855726115465 PSP 18 Aug 2, 2006 Application Note This document demonstrates how to determine the package temperature and thermal mass dependent moisture sensitivity level (MSL) of products to ensure reliable processing of moisture sensitive surface mount components. Comply with these recommendations to maintain package integrity of components during any heat exposure of board soldering and de-soldering. None /docs/en/application-note/AN3298.pdf English documents 151612 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3298.pdf Solder Joint Temperature and Package Peak Temperature /docs/en/application-note/AN3298.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Solder Joint Temperature and Package Peak Temperature 151.6 KB AN3298 N 1154542628855726115465 Data Sheet 1 /secured/assets/documents/en/data-sheet/LS2084A.pdf 2018-04-02 1522659119179715436323 PSP 1 Jun 15, 2021 Data Sheet The LS2084A and LS2044A have eight and four, respectively, Arm® Cortex®-A72 cores built on Armv8-A architecture with high-performance data path acceleration and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and military/aerospace applications. Registration without Disclaimer /secured/assets/documents/en/data-sheet/LS2084A.pdf English documents 1655840 None 980000996212993340 2022-12-07 Y /webapp/Download?colCode=LS2084A LS2084A/LS2044A Data Sheet /secured/assets/documents/en/data-sheet/LS2084A.pdf documents 980000996212993340 Data Sheet N en Extended Y pdf 4 Y N LS2084A/LS2044A Data Sheet 1.7 MB LS2084A N 1522659119179715436323 Errata 1 https://nxp1.sharepoint.com/teams/cext73/SitePages/Home.aspx 2022-02-21 1645462520310720216311 PSP 20 May 22, 2023 Errata The current errata for LS2084/44A, released Feb 2023, Rev 2. It is an NDA document. Please see the Sharepoint site https://nxp1.sharepoint.com/teams/cext73/SitePages/Home.aspx (NDA and NXP-issued invite required), or contact your NXP representative. URL None https://nxp1.sharepoint.com/teams/cext73/SitePages/Home.aspx English documents kb None 155452329886410597 2023-05-23 N https://nxp1.sharepoint.com/teams/cext73/SitePages/Home.aspx LX2084 Errata https://nxp1.sharepoint.com/teams/cext73/SitePages/Home.aspx documents 155452329886410597 Errata N en None Y Y N URL 2 N LX2084 Errata Y LX2084-ERRATA-LINK N https://nxp1.sharepoint.com/teams/cext73/SitePages/Home.aspx 1645462520310720216311 Fact Sheet 1 /docs/en/fact-sheet/LS2084AFS.pdf 2020-08-19 1597863003792722925627 PSP 21 Aug 19, 2020 Fact Sheet The Layerscape LS2044A and LS2084A multicore processors combine four and eight Arm® Cortex®-A72 cores, respectively, with the advanced, high-performance datapath and network peripheral interfaces required for networking, telecom/datacom, wireless infrastructure, military and aerospace applications. None /docs/en/fact-sheet/LS2084AFS.pdf English documents 4512215 None 736675474163315314 2022-12-07 N /docs/en/fact-sheet/LS2084AFS.pdf LAYERSCAPE LS2044A AND LS2084A COMMUNICATIONS PROCESSORS /docs/en/fact-sheet/LS2084AFS.pdf documents 736675474163315314 Fact Sheet N en None Y pdf 0 N N LAYERSCAPE LS2044A AND LS2084A COMMUNICATIONS PROCESSORS 4.5 MB LS2084AFS N 1597863003792722925627 Reference Manual 2 /secured/assets/documents/en/reference-manual/LS2088A_LS2084A_LS2048A_LS2044ARM.pdf 2018-04-12 1523543520051699158347 PSP 2 Sep 28, 2020 Reference Manual The LS2088A, LS2044A, LS2084A, LS2048A can be used for control and dataplane, data path, and advanced IO processing in routers, switches, gateways, and general-purpose embedded computing systems. Like other QorIQ products, the LS2088A’s high level of integration offers significant space, weight, and power benefits compared to multiple discrete devices. Registration without Disclaimer /secured/assets/documents/en/reference-manual/LS2088A_LS2084A_LS2048A_LS2044ARM.pdf English documents 57609863 None 500633505221135046 2023-06-18 Y /webapp/Download?colCode=LS2088ARM QorIQ LS2088A Reference Manual /secured/assets/documents/en/reference-manual/LS2088A_LS2084A_LS2048A_LS2044ARM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 1 Y N QorIQ LS2088A Reference Manual 57.6 MB LS2088ARM N 1523543520051699158347 /docs/en/reference-manual/LS2088ASECRM.pdf 2018-05-07 1525684676209714011650 PSP 3 May 7, 2018 Reference Manual LS2088ASECRM: This manual documents the LS2088A's security engine, the cryptographic acceleration and offloading hardware. None /docs/en/reference-manual/LS2088ASECRM.pdf English documents 7191599 None 500633505221135046 2022-12-07 N /docs/en/reference-manual/LS2088ASECRM.pdf LS2088ASECRM, LS2088A Security (SEC) Reference Manual - Reference Manual /docs/en/reference-manual/LS2088ASECRM.pdf documents 500633505221135046 Reference Manual N en None Y pdf 0 N N LS2088ASECRM, LS2088A Security (SEC) Reference Manual - Reference Manual 7.2 MB LS2088ASECRM N 1525684676209714011650 Supporting Information 1 /docs/en/supporting-information/FSLNISTCAVP.pdf 2016-11-09 1368836090577704535160 PSP 22 Oct 28, 2016 Supporting Information FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. None /docs/en/supporting-information/FSLNISTCAVP.pdf English documents 303546 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1.9 N N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 303.5 KB FSLNISTCAVP N 1368836090577704535160 User Manual 1 /secured/assets/documents/en/user-guide/DPAA2UM.pdf 2020-02-26 1582785451078700466276 PSP 19 Sep 19, 2023 User Manual DPAA2 is a hardware-level networking architecture found on some NXP SoCs. This document provides technical information on this architecture mainly for software developers. Registration without Disclaimer /secured/assets/documents/en/user-guide/DPAA2UM.pdf English documents 5987656 None 309919593431037931 2023-09-21 Y /webapp/Download?colCode=DPAA2UM DPAA2 User Manual /secured/assets/documents/en/user-guide/DPAA2UM.pdf documents 309919593431037931 User Manual N en Extended Y pdf 53 Y N DPAA2 User Manual 6.0 MB DPAA2UM N 1582785451078700466276 White Paper 1 /docs/en/white-paper/VIRTUAL-SOFTWARE-SOLUTIONS-WP.pdf 2018-09-14 1536959379286712399360 PSP 23 Sep 14, 2018 White Paper Traditional WAN services that use enterprise routers and other networking equipment face new competition: managed services with software-defined WAN (SD-WAN) technology and traditional WAN services with network-function virtualization (NFV). None /docs/en/white-paper/VIRTUAL-SOFTWARE-SOLUTIONS-WP.pdf English documents 138002 None 918633085541740938 2022-12-07 N /docs/en/white-paper/VIRTUAL-SOFTWARE-SOLUTIONS-WP.pdf VIRTUAL AND SOFTWARE SOLUTIONS: THE BATTLE FOR ENTERPRISE NETWORK SUPREMACY /docs/en/white-paper/VIRTUAL-SOFTWARE-SOLUTIONS-WP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N N VIRTUAL AND SOFTWARE SOLUTIONS: THE BATTLE FOR ENTERPRISE NETWORK SUPREMACY 138.0 KB VIRTUAL-SOFTWARE-SOLUTIONS-WP N 1536959379286712399360 true Y Products

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