8-Bit I²C-Bus and SMBus I/O Port with Reset | NXP Semiconductors

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8-Bit I²C-Bus and SMBus I/O Port with Reset

PCA9557 Active

The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for SMBus and I²C-bus applications. The PCA9557 consists of an 8-bit input port register, 8-bit output port register, and an I²C-bus/SMBus interface. It has low current consumption and a high-impedance open-drain output pin, IO0.

The system controller can enable the PCA9557's I/O as either input or output by writing to the configuration register. The system controller can also invert the PCA9557 inputs by writing to the active HIGH polarity inversion register. Finally, the system controller can reset the PCA9557 in the event of a time-out by asserting a LOW in the reset input.

The power-on reset puts the registers in their default state and initializes the I²C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part.

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Product Details

Block Diagram

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PCA9557

PCA9557 Block Diagram

PCA9557BS, PCA9557D, PCA9557PW

PCA9557BS, PCA9557D, PCA9557PW

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Features

Key Features

  • Lower voltage, higher performance migration path for the PCA9556
  • 8 general purpose input/output expander/collector
  • Input/output configuration register
  • Active HIGH polarity inversion register
  • I²C-bus and SMBus interface logic
  • Internal power-on reset
  • Noise filter on SCL/SDA inputs
  • Active LOW reset input
  • 3 address pins allowing up to 8 devices on the I²C-bus/SMBus
  • High-impedance open-drain on IO0
  • No glitch on power-up
  • Power-up with all channels configured as inputs
  • Low standby current
  • Operating power supply voltage range of 2.3 V to 5.5 V
  • 5 V tolerant inputs/outputs
  • 0 kHz to 400 kHz clock frequency
  • ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Three packages offered: SO16, TSSOP16, HVQFN16

Buy/Parametrics

2 results

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Part

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CAD Model

No of bits

VDD [min]

VDD [max]

Over volt tolerant

No of supplies

Standby current [typ] (µA)

Max Sink Current per bit (mA)

Max Sink Current, per package (mA)

Source Current per bit (mA)

Reset input pin

Output mode

Input mode: invert option

I2C-bus (kHz)

Footprint body and leads

Package Type

Operating Temperature (°C)

No of Addresses

Remark

PCA9557BS
Data Sheet

8

2.3

5.5

Y

1

0.25

25

100

20

Y

Totem Pole/Open Drain

Y

400

16.81

HVQFN16

-40~85

8

Only bit 0 is open drain

PCA9557PW
Data Sheet

8

2.3

5.5

Y

1

0.25

25

100

20

Y

Totem Pole/Open Drain

Y

400

33.66

TSSOP16

-40~85

8

Only bit 0 is open drain

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Application Note (5)
Brochure (1)
Data Sheet (1)
Package Information (2)
Packing Information (4)
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5 design files

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