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QorIQ® T1042 and T1022 Multicore Communications Processors

T1042
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The QorIQ T1042 quad-core and T1022 dual-core communication processors support two or four integrated 64-bit e5500 Power Architecture® processor cores with high-performance data path acceleration architecture (DPAA) and network peripheral interfaces required for networking and telecommunications.

The T1 family of devices is a scalable, pin-compatible family of communications processors – and offers pin-compatible migration up to the higher-performance QorIQ T2081 device.

Block Diagram

QorIQ T1040/20 and T1042/22 Communication Processors

QorIQ T1040/20 and T1042/22 Communication Processors
Get diagram PDF

Features

Core Complex

  • Two or four e5500 cores, built on Power Architecture technology
  • Up to 1.4 GHz with 64-bit ISA support
  • Three levels of instructions: user, supervisor, hypervisor
  • Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture
  • 256 KB backside L2 cache

Networking Elements

  • SerDes
    • Eight lanes at up to 5 Gbps
    • Supports SGMII, QSGMII, PCIe and SATA
  • Ethernet Interfaces
    • Up to five Gigabit Ethernet interfaces

Accelerators and Memory Control

  • 32/64-bit DDR3L/4 SDRAM memory controller with ECC support
    • Up to 1600 MT/s
  • DPAA Incorporating acceleration for the following functions Packet parsing, classification, and distribution
    • Queue management for scheduling, packet sequencing and congestion management
    • Hardware buffer management for buffer allocation and de-allocation
    • Integrated security acceleration (SEC)
    • Signature detection (PME)

Basic Peripherals and Interconnect

  • CoreNet® platform cache
    • 256 KB shared platform cache
  • Hierarchical interconnect fabric
    • CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet endpoints
  • Additional peripheral interfaces two Serial ATA (SATA 2.0) controllers
    • Two high-speed USB 2.0 controllers with integrated PHYs
    • Enhanced secure digital host controller (SD/MMC/eMMC)
    • Enhanced serial peripheral interface (eSPI)
    • Two I2C controllers
    • Four UARTS
    • Integrated flash controller supporting NAND and NOR flash
  • DMA
    • Dual four channel
    • Up to 5x 1 Gbps Ethernet MACs as part of DPAA
  • QUICC Engine®
    • Support for legacy protocols TDM, HDLC, UART and ISDN
  • High-speed peripheral interfaces
    • Four PCI Express® 2.0 controllers

Additional Features

  • Support for hardware virtualization and partitioning enforcement
    • Extra privileged level for hypervisor support
  • QorIQ® trust architecture
    • Secure boot, secure debug, tamper detection, volatile key storage
  • This product is included in Our product longevity program, with assured supply for a minimum of 10 years after launch

More

Comparison Table

T1020 T1022 T1040 T1042 T2081
CPU2 e55002 e55004 e55004 e55004 e6500 (dual-threaded)
Core Frequency1200-1400MHz1200-1400MHz1200-1400MHz1200-1400MHz1500-1800MHz
DDR I/F1x DDR3L/4 to 1600MT/s1x DDR3L/4 to 1600MT/s1x DDR3L/4 to 1600MT/s1x DDR3L/4 to 1600MT/s1x DDR3/3L to 2133MT/s
Ethernet (with IEEE1588v2)8-Port GE Switch + 4x 1GE5x 1GE8-Port GE Switch + 4x 1GE5x 1GE2x 1/10GE + 6x 1GE
SERDES8 lanes (5GHz)8 lanes (5GHz)8 lanes (5GHz)8 lanes (5GHz)8 lanes (10GHz)
Package Pin Compatible

Buy/Parametrics

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Package Type

Package Termination Count

Core: Number of cores (SPEC)

Core Type

Operating Frequency [Max] (MHz)

Junction Temperature (Min to Max) (℃)

L2 Cache (Max) (KB)

Ethernet Type

PCIe

External Memory Supported

Typical Power

T1022NSE7MQB
Data Sheet

Active

100 @ US$70.52

FBGA780

780

2

e5500

1200

0 to 105

256

10/100 BaseT, 1G, 2.5G

—

DDR3L SDRAM, DDR4 SDRAM

4.5

T1022NSE7PQB
Data Sheet

Active

100 @ US$84.62

FBGA780

780

2

e5500

1400

0 to 105

256

10/100 BaseT, 1G, 2.5G

—

DDR3L SDRAM, DDR4 SDRAM

4.5

T1022NSE7PQPB
Data Sheet

Active

100 @ US$97.32

FBGA780

780

2

e5500

1400

0 to 105

256

10/100 BaseT, 1G, 2.5G

4

DDR3L SDRAM, DDR4 SDRAM

4

T1022NSE7WQB
Data Sheet

Active

100 @ US$84.62

FBGA780

780

2

e5500

1500

0 to 105

256

10/100 BaseT, 1G, 2.5G

4

DDR3L SDRAM, DDR4 SDRAM

4

T1022NSN7MQB
Data Sheet

Active

100 @ US$67.18

FBGA780

780

2

e5500

1200

0 to 105

256

10/100 BaseT, 1G, 2.5G

—

DDR3L SDRAM, DDR4 SDRAM

4.5

T1022NSN7PQB
Data Sheet

Active

100 @ US$80.59

FBGA780

780

2

e5500

1400

0 to 105

256

10/100 BaseT, 1G, 2.5G

—

DDR3L SDRAM, DDR4 SDRAM

4.5

T1022NXE7MQB
Data Sheet

Active

100 @ US$81.12

FBGA780

780

2

e5500

1200

-40 to 105

256

10/100 BaseT, 1G, 2.5G

—

DDR3 SDRAM, DDR4 SDRAM

4.5

T1022NXE7PQB
Data Sheet

Active

100 @ US$97.33

FBGA780

780

2

e5500

1400

-40 to 105

256

10/100 BaseT, 1G, 2.5G

—

DDR3 SDRAM, DDR4 SDRAM

4.5

T1022NXN7MQB
Data Sheet

Active

100 @ US$77.24

FBGA780

780

2

e5500

1200

-40 to 105

256

10/100 BaseT, 1G, 2.5G

4

DDR3L SDRAM, DDR4 SDRAM

4

T1022NXN7PQB
Data Sheet

Active

100 @ US$92.69

FBGA780

780

2

e5500

1400

-40 to 105

256

10/100 BaseT, 1G, 2.5G

—

DDR3 SDRAM, DDR4 SDRAM

4.5

N true 0 PSPT1042en 23 Application Note Application Note t789 11 Data Sheet Data Sheet t520 1 Fact Sheet Fact Sheet t523 1 Product Brief Product Brief t532 1 Reference Manual Reference Manual t877 5 Supporting Information Supporting Information t531 1 User Guide User Guide t792 1 White Paper White Paper t530 2 en_US 1 1 1 Chinese 1349276610362740017554zh PSP 289.7 KB None None documents None 1349276610362740017554 /docs/zh/fact-sheet/T1FAMILYFS.pdf 289708 /docs/zh/fact-sheet/T1FAMILYFS.pdf T1FAMILYFS documents N N 2012-10-09 QorIQ T Series T1020/22 and T1040/42 Processors - Fact Sheet /docs/zh/fact-sheet/T1FAMILYFS.pdf /docs/zh/fact-sheet/T1FAMILYFS.pdf /docs/zh/fact-sheet/T1FAMILYFS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 N zh 736675474163315314 Fact Sheet N QorIQ<sup>®</sup> T系列T1020/22和T1040/42处理器 - 简介 2 English The QorIQ<sup>&#174;</sup> T1 family of communications processors combines up to four 64-bit cores, built on Power Architecture&#174; technology, with high-performance data path acceleration architecture (DPAA) and network peripheral bus interfaces required for networking and telecommunications. 1349276610362740017554 PSP 289.7 KB None None documents None 1349276610362740017554 /docs/en/fact-sheet/T1FAMILYFS.pdf 289708 /docs/en/fact-sheet/T1FAMILYFS.pdf T1FAMILYFS N N 2012-10-09 QorIQ T Series T1020/22 and T1040/42 Processors - Fact Sheet /docs/en/fact-sheet/T1FAMILYFS.pdf /docs/en/fact-sheet/T1FAMILYFS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 pdf N en Feb 14, 2017 Fact Sheet t523 Fact Sheet Fact Sheet N QorIQ T Series T1020/22 and T1040/42 Processors - Fact Sheet false en_US en Data Sheet Data Sheet 1 2 2 English The T1042 QorIQ<sup>&#174;</sup> advanced multicore processor combines with high-performance data path acceleration and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and military/aerospace applications. 1422123512741712864354 PSP 1.5 MB Registration without Disclaimer None documents Extended 1422123512741712864354 /secured/assets/documents/en/data-sheet/T1042.pdf 1528067 /secured/assets/documents/en/data-sheet/T1042.pdf T1042 documents Y N 2015-01-24 QorIQ<sup>&#174;</sup> T1042, T1022 Data Sheet /webapp/Download?colCode=T1042 /secured/assets/documents/en/data-sheet/T1042.pdf Data Sheet N 980000996212993340 2023-06-18 pdf Y en Jun 29, 2015 980000996212993340 Data Sheet Y N QorIQ<sup>&#174;</sup> T1042, T1022 Data Sheet Reference Manual Reference Manual 5 3 2 English The T1040 quad-core and T1020 dual-core QorIQ processor combines four or two 64-bit ISA Power Architecture® processor cores with high-performance DPAA, integrated 8-port Gigabit Ethernet switch and network peripheral bus interfaces required for networking and telecommunications. 1422074312466723542634 PSP 21.2 MB Registration without Disclaimer None documents Extended 1422074312466723542634 /secured/assets/documents/en/reference-manual/T1040RM.pdf 21193423 /secured/assets/documents/en/reference-manual/T1040RM.pdf T1040RM documents Y N 2017-03-06 QorIQ T1040 Reference Manual /webapp/Download?colCode=T1040RM /secured/assets/documents/en/reference-manual/T1040RM.pdf Reference Manual N 500633505221135046 2023-06-18 pdf Y en Jun 5, 2020 500633505221135046 Reference Manual Y N QorIQ T1040 Reference Manual 4 9 English This QEIWRM reference manual defines the functionality of the QUICC Engine<sup>&#174;</sup> block, a versatile RISC-based communication processor. The QUICC Engine block supports multiple external interfaces and protocols independently from the core processor in an integrated processing device. Use this reference manual in conjunction with your device reference manual to implement the QUICC Engine functionality. 1233608188787709580857 PSP 13.4 MB Registration without Disclaimer None documents Extended 1233608188787709580857 /secured/assets/documents/en/reference-manual/QEIWRM.pdf 13369144 /secured/assets/documents/en/reference-manual/QEIWRM.pdf QEIWRM documents Y N 2016-10-31 QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual /webapp/Download?colCode=QEIWRM /secured/assets/documents/en/reference-manual/QEIWRM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en May 3, 2018 500633505221135046 Reference Manual Y N QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual 5 4 English e5500RM: This document includes the register model, instruction model, MMU, memory subsystem, debug and performance monitor facilities of the e5500. 1320675592951722488289 PSP 3.7 MB Registration without Disclaimer None documents Extended 1320675592951722488289 /secured/assets/documents/en/reference-manual/e5500RM.pdf 3661467 /secured/assets/documents/en/reference-manual/e5500RM.pdf E5500RM documents Y N 2011-11-07 e5500RM, e5500 Core Reference Manual with Updates - Reference Manual /webapp/Download?colCode=E5500RM /secured/assets/documents/en/reference-manual/e5500RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jul 28, 2015 500633505221135046 Reference Manual Y N e5500RM, e5500 Core Reference Manual with Updates - Reference Manual 6 0 English T1040DPAArm: The QorIQ<sup>®</sup> data path acceleration architecture (DPAA) provides the infrastructure to support simplified sharing of networking interfaces and accelerators by multiple CPU cores. 1422990991419695404861 PSP 18.4 MB Registration without Disclaimer None documents Extended 1422990991419695404861 /secured/assets/documents/en/reference-manual/T1040DPAARM.pdf 18442299 /secured/assets/documents/en/reference-manual/T1040DPAARM.pdf T1040DPAARM documents Y N 2016-10-31 T1040DPAArm, T1040 QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual - Reference Manual /webapp/Download?colCode=T1040DPAARM /secured/assets/documents/en/reference-manual/T1040DPAARM.pdf Reference Manual N 500633505221135046 2023-06-18 pdf Y en Feb 3, 2015 500633505221135046 Reference Manual Y N T1040DPAArm, T1040 QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual - Reference Manual 7 0 English T1040SECRM: This manual documents the T1040's security engine, the cryptographic acceleration and offloading hardware. 1422046978213700573482 PSP 12.8 MB Registration without Disclaimer None documents Extended 1422046978213700573482 /secured/assets/documents/en/reference-manual/T1040SECRM.pdf 12798684 /secured/assets/documents/en/reference-manual/T1040SECRM.pdf T1040SECRM documents Y N 2015-01-23 T1040SECRM, T1040 Security (SEC) Reference Manual - Reference Manual /webapp/Download?colCode=T1040SECRM /secured/assets/documents/en/reference-manual/T1040SECRM.pdf Reference Manual N 500633505221135046 2023-06-18 pdf Y en Jan 22, 2015 500633505221135046 Reference Manual Y N T1040SECRM, T1040 Security (SEC) Reference Manual - Reference Manual Application Note Application Note 11 8 3 English AN5097: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR4 memory subsystem. 1428008859060729157318 PSP 1.1 MB Registration without Disclaimer None documents Extended 1428008859060729157318 /secured/assets/documents/en/application-note/AN5097.pdf 1120906 /secured/assets/documents/en/application-note/AN5097.pdf AN5097 documents Y N 2016-10-31 Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces /webapp/Download?colCode=AN5097 /secured/assets/documents/en/application-note/AN5097.pdf Application Note N 645036621402383989 2024-12-18 pdf Y en Jul 28, 2023 645036621402383989 Application Note Y N Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces 9 0 English AN12105: This document can be used to deploy U-Boot directly to the DDR of QorIQ T1040D4RDB using CodeWarrior and allows the user to initialize the board. 1523341236346699404047 PSP 10.9 MB Registration without Disclaimer None documents Extended 1523341236346699404047 /secured/assets/documents/en/application-note/AN12105.pdf 10918301 /secured/assets/documents/en/application-note/AN12105.pdf AN12105 documents Y N 2018-04-09 U-Boot Bring Up using CodeWarrior on T1040D4RDB Application Note /webapp/Download?colCode=AN12105 /secured/assets/documents/en/application-note/AN12105.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Apr 9, 2018 645036621402383989 Application Note Y N U-Boot Bring Up using CodeWarrior on T1040D4RDB Application Note 10 0 English Explains how to design a common board between T1024 and T1022 QorIQ communications processor by achieving hardware compatibility. 1500885517617703401746 PSP 401.1 KB None None documents None 1500885517617703401746 /docs/en/application-note/AN4829.pdf 401068 /docs/en/application-note/AN4829.pdf AN4829 documents N N 2017-07-24 AN4829, Common Board Design Between T1024 and T1022 Processor - Application Note /docs/en/application-note/AN4829.pdf /docs/en/application-note/AN4829.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jul 24, 2017 645036621402383989 Application Note N AN4829, Common Board Design Between T1024 and T1022 Processor - Application Note 11 0 English Provides comparison between QorIQ P1 series (P1010, P1020, P1022) and T1 series (T1024, T1014, T1023, T1013, T1040, T1020, T1042, T1022) devices. 1500876825316705874194 PSP 349.9 KB None None documents None 1500876825316705874194 /docs/en/application-note/AN5079.pdf 349919 /docs/en/application-note/AN5079.pdf AN5079 documents N N 2017-07-23 AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note /docs/en/application-note/AN5079.pdf /docs/en/application-note/AN5079.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jul 24, 2017 645036621402383989 Application Note N AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note 12 2 English AN5119: This application note is a companion document to the SerDes Configuration & Validation Tool User Guide. It is provided to assist those engineers wishing to use the Tx Equalization, Built-In Self Test (BIST), and Jitter Scope test features of the QCVS SerDes validation tool. The 10 G SerDes block is the basis for describing the technical topics. The 10 G SerDes is in the T4240, B4860, T2080, P5040, and T1xx QorIQ multicore processors families. 1577097353709690091820 PSP 426.5 KB None None documents None 1577097353709690091820 /docs/en/application-note/AN5119.pdf 426530 /docs/en/application-note/AN5119.pdf AN5119 documents N N 2019-12-23 SerDes Configuration and Validation Tool Companion Application Note /docs/en/application-note/AN5119.pdf /docs/en/application-note/AN5119.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jan 29, 2016 645036621402383989 Application Note Y N SerDes Configuration and Validation Tool Companion Application Note 13 1 English AN4825: This document provides recommendations for new designs based on the T1040, which is an advanced, multicore processor that combines four e5500 processor cores built on Power Architecture&#174;, with high-performance datapath acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and mil/aerospace applications. 1422594417962727536636 PSP 862.5 KB Registration without Disclaimer documents Extended 1422594417962727536636 /secured/assets/documents/en/application-note/AN4825.pdf 862489 /secured/assets/documents/en/application-note/AN4825.pdf AN4825 documents Y N 2015-01-29 AN4825, T1040 Family Design Checklist - Application Note /webapp/Download?colCode=AN4825 /secured/assets/documents/en/application-note/AN4825.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Apr 9, 2015 645036621402383989 Application Note N AN4825, T1040 Family Design Checklist - Application Note 14 0 English AN4848: The PCIe bus has been gaining popularity over the last decade. Almost all of Our mid and high-end devices offer at least one PCIe port as part of their standard SOC. Most of them offer more than a single port, thus eliminating the need for an external PCIe switch. 1390372586014711432307 PSP 1.2 MB Registration without Disclaimer None documents Extended 1390372586014711432307 /secured/assets/documents/en/application-note/AN4848.pdf 1207848 /secured/assets/documents/en/application-note/AN4848.pdf AN4848 documents Y N 2016-10-31 AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes /webapp/Download?colCode=AN4848 /secured/assets/documents/en/application-note/AN4848.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Jan 21, 2014 645036621402383989 Application Note N AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes 15 6 English AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. 1264793052715706871063 PSP 547.7 KB Registration without Disclaimer None documents Extended 1264793052715706871063 /secured/assets/documents/en/application-note/AN3940.pdf 547662 /secured/assets/documents/en/application-note/AN3940.pdf AN3940 documents Y N 2016-10-31 AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /webapp/Download?colCode=AN3940 /secured/assets/documents/en/application-note/AN3940.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Nov 25, 2013 645036621402383989 Application Note Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 16 Rev. 0 English This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. 1305312143395731535528 PSP 577.2 KB Registration without Disclaimer None documents Extended 1305312143395731535528 /secured/assets/documents/en/application-note/AN4311.pdf 577164 /secured/assets/documents/en/application-note/AN4311.pdf AN4311 documents Y N 2016-10-31 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /webapp/Download?colCode=AN4311 /secured/assets/documents/en/application-note/AN4311.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 13, 2011 645036621402383989 Application Note Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 17 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939 /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors 18 0 English High-level data link control (HDLC) is widely used in the telecommunications and networking industries. NXP&#8217;s PowerQUICC&#8482; communications processors have extensive support for HDLC protocol through the communications processor module (CPM) and QUICC Engine&#8482; technologies.&#13;&#10;&#13;&#10;This application note explains how NXP&#8217;s existing&#13;&#10;PowerQUICC communications processors use the CPM and QUICC Engine technologies to support the HDLC protocol and provides HDLC e 1258066893562722616236 PSP 496.6 KB None None documents None 1258066893562722616236 /docs/en/application-note/AN3966.pdf 496625 /docs/en/application-note/AN3966.pdf AN3966 documents N 2016-10-31 PowerQUICC™ HDLC Support and Example Code /docs/en/application-note/AN3966.pdf /docs/en/application-note/AN3966.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 10, 2009 645036621402383989 Application Note N PowerQUICC™ HDLC Support and Example Code User Guide User Guide 1 19 1 Y English https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html Y 1576719019599707128294 PSP None None documents None 1576719019599707128294 /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC SPECTRE-MELTDOWN-POWER-ISA-DOC documents N N Y 2019-12-18 Spectre and Meltdown Updates for Power ISA Cores https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC User Guide N 132339537837198660 Y /bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html 2022-12-07 N en Nov 14, 2019 132339537837198660 User Guide Y N Spectre and Meltdown Updates for Power ISA Cores Product Brief Product Brief 1 20 0 English The T1040 QorIQ<sup>&#174;</sup> communication processor combines four 64-bit ISA Power architecture&#8482; processor cores with highperformance datapath acceleration logic, integrated 8-port Gigabit Ethernet switch, and network peripheral bus interfaces??required for networking, and telecommunications. 1396536601926689998231 PSP 222.3 KB Registration without Disclaimer None documents Extended 1396536601926689998231 /secured/assets/documents/en/product-brief/T1040PB.pdf 222276 /secured/assets/documents/en/product-brief/T1040PB.pdf T1040PB documents Y N 2014-04-03 T1040/20 and T1042/22 Product Brief /webapp/Download?colCode=T1040PB /secured/assets/documents/en/product-brief/T1040PB.pdf Product Brief N 899114358132306053 2022-12-07 pdf Y en Apr 2, 2014 899114358132306053 Product Brief Y N T1040/20 and T1042/22 Product Brief Supporting Information Supporting Information 1 21 1.9 English FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. 1368836090577704535160 PSP 303.5 KB None None documents None 1368836090577704535160 /docs/en/supporting-information/FSLNISTCAVP.pdf 303546 /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP documents N N 2016-11-09 FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf /docs/en/supporting-information/FSLNISTCAVP.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 28, 2016 371282830530968666 Supporting Information Y N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper White Paper White Paper 2 22 0 English In this paper, we present the mitigations for Spectre variant 1 and Spectre variant 2 for NXP PowerPC processors. The NXP PowerPC processors are not vulnerable to the Meltdown attack, Spectre variant 1.1/1.2, or Spectre variant 4. 1580452712610724357770 PSP 317.1 KB None None documents None 1580452712610724357770 /docs/en/white-paper/SPECTREPPCWP.pdf 317053 /docs/en/white-paper/SPECTREPPCWP.pdf SPECTREPPCWP documents N N 2020-01-30 Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper /docs/en/white-paper/SPECTREPPCWP.pdf /docs/en/white-paper/SPECTREPPCWP.pdf White Paper N 918633085541740938 2022-12-07 pdf N en Jan 30, 2020 918633085541740938 White Paper Y N Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper 23 0 English QORIQPMWP: This document describes how Power Management technologies will play a more important role in controlling or reducing power consumption of electronic systems. 1419964678458711207150 PSP 1.4 MB None None documents None 1419964678458711207150 /docs/en/white-paper/QORIQPMWP.pdf 1418055 /docs/en/white-paper/QORIQPMWP.pdf QORIQPMWP documents N N 2017-03-30 QORIQPMWP, QorIQ Power Management - White Paper /docs/en/white-paper/QORIQPMWP.pdf /docs/en/white-paper/QORIQPMWP.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Mar 30, 2017 918633085541740938 White Paper N QORIQPMWP, QorIQ Power Management - White Paper false 0 T1042 downloads en true 1 Y PSP Application Note 11 /secured/assets/documents/en/application-note/AN5097.pdf 2016-10-31 1428008859060729157318 PSP 8 Jul 28, 2023 Application Note AN5097: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR4 memory subsystem. Registration without Disclaimer /secured/assets/documents/en/application-note/AN5097.pdf English documents 1120906 None 645036621402383989 2024-12-18 Y /webapp/Download?colCode=AN5097 Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces /secured/assets/documents/en/application-note/AN5097.pdf documents 645036621402383989 Application Note N en Extended Y pdf 3 Y N Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces 1.1 MB AN5097 N 1428008859060729157318 /secured/assets/documents/en/application-note/AN12105.pdf 2018-04-09 1523341236346699404047 PSP 9 Apr 9, 2018 Application Note AN12105: This document can be used to deploy U-Boot directly to the DDR of QorIQ T1040D4RDB using CodeWarrior and allows the user to initialize the board. Registration without Disclaimer /secured/assets/documents/en/application-note/AN12105.pdf English documents 10918301 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN12105 U-Boot Bring Up using CodeWarrior on T1040D4RDB Application Note /secured/assets/documents/en/application-note/AN12105.pdf documents 645036621402383989 Application Note N en Extended Y pdf 0 Y N U-Boot Bring Up using CodeWarrior on T1040D4RDB Application Note 10.9 MB AN12105 N 1523341236346699404047 /docs/en/application-note/AN4829.pdf 2017-07-24 1500885517617703401746 PSP 10 Jul 24, 2017 Application Note Explains how to design a common board between T1024 and T1022 QorIQ communications processor by achieving hardware compatibility. None /docs/en/application-note/AN4829.pdf English documents 401068 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4829.pdf AN4829, Common Board Design Between T1024 and T1022 Processor - Application Note /docs/en/application-note/AN4829.pdf documents 645036621402383989 Application Note N en None pdf 0 N N AN4829, Common Board Design Between T1024 and T1022 Processor - Application Note 401.1 KB AN4829 N 1500885517617703401746 /docs/en/application-note/AN5079.pdf 2017-07-23 1500876825316705874194 PSP 11 Jul 24, 2017 Application Note Provides comparison between QorIQ P1 series (P1010, P1020, P1022) and T1 series (T1024, T1014, T1023, T1013, T1040, T1020, T1042, T1022) devices. None /docs/en/application-note/AN5079.pdf English documents 349919 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5079.pdf AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note /docs/en/application-note/AN5079.pdf documents 645036621402383989 Application Note N en None pdf 0 N N AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note 349.9 KB AN5079 N 1500876825316705874194 /docs/en/application-note/AN5119.pdf 2019-12-23 1577097353709690091820 PSP 12 Jan 29, 2016 Application Note AN5119: This application note is a companion document to the SerDes Configuration & Validation Tool User Guide. It is provided to assist those engineers wishing to use the Tx Equalization, Built-In Self Test (BIST), and Jitter Scope test features of the QCVS SerDes validation tool. The 10 G SerDes block is the basis for describing the technical topics. The 10 G SerDes is in the T4240, B4860, T2080, P5040, and T1xx QorIQ multicore processors families. None /docs/en/application-note/AN5119.pdf English documents 426530 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5119.pdf SerDes Configuration and Validation Tool Companion Application Note /docs/en/application-note/AN5119.pdf documents 645036621402383989 Application Note N en None Y pdf 2 N N SerDes Configuration and Validation Tool Companion Application Note 426.5 KB AN5119 N 1577097353709690091820 /secured/assets/documents/en/application-note/AN4825.pdf 2015-01-29 1422594417962727536636 PSP 13 Apr 9, 2015 Application Note AN4825: This document provides recommendations for new designs based on the T1040, which is an advanced, multicore processor that combines four e5500 processor cores built on Power Architecture&#174;, with high-performance datapath acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and mil/aerospace applications. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4825.pdf English documents 862489 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4825 AN4825, T1040 Family Design Checklist - Application Note /secured/assets/documents/en/application-note/AN4825.pdf documents 645036621402383989 Application Note N en Extended pdf 1 Y N AN4825, T1040 Family Design Checklist - Application Note 862.5 KB AN4825 N 1422594417962727536636 /secured/assets/documents/en/application-note/AN4848.pdf 2016-10-31 1390372586014711432307 PSP 14 Jan 21, 2014 Application Note AN4848: The PCIe bus has been gaining popularity over the last decade. Almost all of Our mid and high-end devices offer at least one PCIe port as part of their standard SOC. Most of them offer more than a single port, thus eliminating the need for an external PCIe switch. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4848.pdf English documents 1207848 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4848 AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes /secured/assets/documents/en/application-note/AN4848.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes 1.2 MB AN4848 N 1390372586014711432307 /secured/assets/documents/en/application-note/AN3940.pdf 2016-10-31 1264793052715706871063 PSP 15 Nov 25, 2013 Application Note AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3940.pdf English documents 547662 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3940 AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /secured/assets/documents/en/application-note/AN3940.pdf documents 645036621402383989 Application Note N en Extended Y pdf 6 Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 547.7 KB AN3940 N 1264793052715706871063 /secured/assets/documents/en/application-note/AN4311.pdf 2016-10-31 1305312143395731535528 PSP 16 May 13, 2011 Application Note This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4311.pdf English documents 577164 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4311 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /secured/assets/documents/en/application-note/AN4311.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev. 0 Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 577.2 KB AN4311 N 1305312143395731535528 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 17 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939 DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 /docs/en/application-note/AN3966.pdf 2016-10-31 1258066893562722616236 PSP 18 Nov 10, 2009 Application Note High-level data link control (HDLC) is widely used in the telecommunications and networking industries. NXP&#8217;s PowerQUICC&#8482; communications processors have extensive support for HDLC protocol through the communications processor module (CPM) and QUICC Engine&#8482; technologies.&#13;&#10;&#13;&#10;This application note explains how NXP&#8217;s existing&#13;&#10;PowerQUICC communications processors use the CPM and QUICC Engine technologies to support the HDLC protocol and provides HDLC e None /docs/en/application-note/AN3966.pdf English documents 496625 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3966.pdf PowerQUICC™ HDLC Support and Example Code /docs/en/application-note/AN3966.pdf documents 645036621402383989 Application Note N en None pdf 0 N PowerQUICC™ HDLC Support and Example Code 496.6 KB AN3966 N 1258066893562722616236 Data Sheet 1 /secured/assets/documents/en/data-sheet/T1042.pdf 2015-01-24 1422123512741712864354 PSP 2 Jun 29, 2015 Data Sheet The T1042 QorIQ<sup>&#174;</sup> advanced multicore processor combines with high-performance data path acceleration and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and military/aerospace applications. Registration without Disclaimer /secured/assets/documents/en/data-sheet/T1042.pdf English documents 1528067 None 980000996212993340 2023-06-18 Y /webapp/Download?colCode=T1042 QorIQ<sup>&#174;</sup> T1042, T1022 Data Sheet /secured/assets/documents/en/data-sheet/T1042.pdf documents 980000996212993340 Data Sheet N en Extended Y pdf 2 Y N QorIQ<sup>&#174;</sup> T1042, T1022 Data Sheet 1.5 MB T1042 N 1422123512741712864354 Fact Sheet 1 /docs/en/fact-sheet/T1FAMILYFS.pdf 2012-10-09 1349276610362740017554 PSP 1 Feb 14, 2017 Fact Sheet Fact Sheet The QorIQ<sup>&#174;</sup> T1 family of communications processors combines up to four 64-bit cores, built on Power Architecture&#174; technology, with high-performance data path acceleration architecture (DPAA) and network peripheral bus interfaces required for networking and telecommunications. None /docs/en/fact-sheet/T1FAMILYFS.pdf English 289708 None Fact Sheet 2022-12-07 N /docs/en/fact-sheet/T1FAMILYFS.pdf QorIQ T Series T1020/22 and T1040/42 Processors - Fact Sheet /docs/en/fact-sheet/T1FAMILYFS.pdf documents 736675474163315314 Fact Sheet N Y en None t523 pdf 2 N N QorIQ T Series T1020/22 and T1040/42 Processors - Fact Sheet 289.7 KB T1FAMILYFS N 1349276610362740017554 Product Brief 1 /secured/assets/documents/en/product-brief/T1040PB.pdf 2014-04-03 1396536601926689998231 PSP 20 Apr 2, 2014 Product Brief The T1040 QorIQ<sup>&#174;</sup> communication processor combines four 64-bit ISA Power architecture&#8482; processor cores with highperformance datapath acceleration logic, integrated 8-port Gigabit Ethernet switch, and network peripheral bus interfaces??required for networking, and telecommunications. Registration without Disclaimer /secured/assets/documents/en/product-brief/T1040PB.pdf English documents 222276 None 899114358132306053 2022-12-07 Y /webapp/Download?colCode=T1040PB T1040/20 and T1042/22 Product Brief /secured/assets/documents/en/product-brief/T1040PB.pdf documents 899114358132306053 Product Brief N en Extended Y pdf 0 Y N T1040/20 and T1042/22 Product Brief 222.3 KB T1040PB N 1396536601926689998231 Reference Manual 5 /secured/assets/documents/en/reference-manual/T1040RM.pdf 2017-03-06 1422074312466723542634 PSP 3 Jun 5, 2020 Reference Manual The T1040 quad-core and T1020 dual-core QorIQ processor combines four or two 64-bit ISA Power Architecture® processor cores with high-performance DPAA, integrated 8-port Gigabit Ethernet switch and network peripheral bus interfaces required for networking and telecommunications. Registration without Disclaimer /secured/assets/documents/en/reference-manual/T1040RM.pdf English documents 21193423 None 500633505221135046 2023-06-18 Y /webapp/Download?colCode=T1040RM QorIQ T1040 Reference Manual /secured/assets/documents/en/reference-manual/T1040RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 2 Y N QorIQ T1040 Reference Manual 21.2 MB T1040RM N 1422074312466723542634 /secured/assets/documents/en/reference-manual/QEIWRM.pdf 2016-10-31 1233608188787709580857 PSP 4 May 3, 2018 Reference Manual This QEIWRM reference manual defines the functionality of the QUICC Engine<sup>&#174;</sup> block, a versatile RISC-based communication processor. The QUICC Engine block supports multiple external interfaces and protocols independently from the core processor in an integrated processing device. Use this reference manual in conjunction with your device reference manual to implement the QUICC Engine functionality. Registration without Disclaimer /secured/assets/documents/en/reference-manual/QEIWRM.pdf English documents 13369144 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=QEIWRM QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual /secured/assets/documents/en/reference-manual/QEIWRM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 9 Y N QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual 13.4 MB QEIWRM N 1233608188787709580857 /secured/assets/documents/en/reference-manual/e5500RM.pdf 2011-11-07 1320675592951722488289 PSP 5 Jul 28, 2015 Reference Manual e5500RM: This document includes the register model, instruction model, MMU, memory subsystem, debug and performance monitor facilities of the e5500. Registration without Disclaimer /secured/assets/documents/en/reference-manual/e5500RM.pdf English documents 3661467 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=E5500RM e5500RM, e5500 Core Reference Manual with Updates - Reference Manual /secured/assets/documents/en/reference-manual/e5500RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 4 Y N e5500RM, e5500 Core Reference Manual with Updates - Reference Manual 3.7 MB E5500RM N 1320675592951722488289 /secured/assets/documents/en/reference-manual/T1040DPAARM.pdf 2016-10-31 1422990991419695404861 PSP 6 Feb 3, 2015 Reference Manual T1040DPAArm: The QorIQ<sup>®</sup> data path acceleration architecture (DPAA) provides the infrastructure to support simplified sharing of networking interfaces and accelerators by multiple CPU cores. Registration without Disclaimer /secured/assets/documents/en/reference-manual/T1040DPAARM.pdf English documents 18442299 None 500633505221135046 2023-06-18 Y /webapp/Download?colCode=T1040DPAARM T1040DPAArm, T1040 QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual - Reference Manual /secured/assets/documents/en/reference-manual/T1040DPAARM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 0 Y N T1040DPAArm, T1040 QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual - Reference Manual 18.4 MB T1040DPAARM N 1422990991419695404861 /secured/assets/documents/en/reference-manual/T1040SECRM.pdf 2015-01-23 1422046978213700573482 PSP 7 Jan 22, 2015 Reference Manual T1040SECRM: This manual documents the T1040's security engine, the cryptographic acceleration and offloading hardware. Registration without Disclaimer /secured/assets/documents/en/reference-manual/T1040SECRM.pdf English documents 12798684 None 500633505221135046 2023-06-18 Y /webapp/Download?colCode=T1040SECRM T1040SECRM, T1040 Security (SEC) Reference Manual - Reference Manual /secured/assets/documents/en/reference-manual/T1040SECRM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 0 Y N T1040SECRM, T1040 Security (SEC) Reference Manual - Reference Manual 12.8 MB T1040SECRM N 1422046978213700573482 Supporting Information 1 /docs/en/supporting-information/FSLNISTCAVP.pdf 2016-11-09 1368836090577704535160 PSP 21 Oct 28, 2016 Supporting Information FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. None /docs/en/supporting-information/FSLNISTCAVP.pdf English documents 303546 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1.9 N N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 303.5 KB FSLNISTCAVP N 1368836090577704535160 User Guide 1 /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC 2019-12-18 https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html /bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html Y Y 1576719019599707128294 PSP 19 Nov 14, 2019 User Guide None /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC English Y documents Y None 132339537837198660 2022-12-07 N https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html Spectre and Meltdown Updates for Power ISA Cores /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC documents 132339537837198660 User Guide N en None Y 1 N N Spectre and Meltdown Updates for Power ISA Cores SPECTRE-MELTDOWN-POWER-ISA-DOC N 1576719019599707128294 White Paper 2 /docs/en/white-paper/SPECTREPPCWP.pdf 2020-01-30 1580452712610724357770 PSP 22 Jan 30, 2020 White Paper In this paper, we present the mitigations for Spectre variant 1 and Spectre variant 2 for NXP PowerPC processors. The NXP PowerPC processors are not vulnerable to the Meltdown attack, Spectre variant 1.1/1.2, or Spectre variant 4. None /docs/en/white-paper/SPECTREPPCWP.pdf English documents 317053 None 918633085541740938 2022-12-07 N /docs/en/white-paper/SPECTREPPCWP.pdf Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper /docs/en/white-paper/SPECTREPPCWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N N Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper 317.1 KB SPECTREPPCWP N 1580452712610724357770 /docs/en/white-paper/QORIQPMWP.pdf 2017-03-30 1419964678458711207150 PSP 23 Mar 30, 2017 White Paper QORIQPMWP: This document describes how Power Management technologies will play a more important role in controlling or reducing power consumption of electronic systems. None /docs/en/white-paper/QORIQPMWP.pdf English documents 1418055 None 918633085541740938 2023-06-19 N /docs/en/white-paper/QORIQPMWP.pdf QORIQPMWP, QorIQ Power Management - White Paper /docs/en/white-paper/QORIQPMWP.pdf documents 918633085541740938 White Paper N en None pdf 0 N N QORIQPMWP, QorIQ Power Management - White Paper 1.4 MB QORIQPMWP N 1419964678458711207150 true Y Products

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