TJA1153A Secure HS-CAN Transceiver

TJA1153A Secure HS-CAN Transceiver | NXP Semiconductors

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NXP's new secure CAN transceiver TJA1153A provides a seamless and very cost-effective solution for securing classical CAN and CAN FD communication without cryptography. The TJA1153A belongs to a new generation of automotive high-speed CAN/CAN FD transceivers, offering security functions. It provides an interface between a classical CAN or CAN FD protocol controller and the physical two-wire CAN bus. As long as no security incidents have been detected, the TJA1153A behaves like a standard CAN transceiver with Sleep mode.

The security incidents that can be detected and contained are:

Flooding the bus from the local node
Transmitting a CAN message with an identifier that has not been assigned to the local node for transmission
Receiving a CAN message from a remote host with an identifier that is identical to one uniquely assigned to this local node
Tampered messages

Product Details

Block Diagram

TJA1153 Application Block Diagram

Get diagram PDF

Features

General

The TJA1153A is a secure HS-CAN transceiver with Sleep mode and a V_IO supply pin. The V_IO pin allows for direct interfacing with 3.3 V and 5 V microcontrollers
ISO 11898-1:2015, ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5 compliant
Operates in classical CAN and CAN FD systems with arbitration phase bit rate set at 125 kbit/s, 250 kbit/s or 500 kbit/s
For arbitration bit rates of 250 kbit/s and 500 kbit/s, the fast phase bit rate can be set to two or four times the arbitration bit rate
AEC-Q100 Rev-G qualified (grade 1)
Low electromagnetic emission (EME) and high electromagnetic immunity (EMI)
HVSON14 plastic small outline package

System Control and Diagnostic Features

Mode control via dedicated control pins EN and STB_N
Overtemperature shutdown

Security Features

Spoofing protection
Flooding protection
Tamper protection

Predictable and Fail-Safe Behavior

Functional behavior predictable under all supply conditions
Transceiver disengages from bus when not powered (zero load)
Transmit data (TXD) dominant time-out function
Internal biasing of TXD, EN and STB_N input pins

Protection

High ESD handling capability on the bus pins (8 kV HBM)
Bus and VBAT pins protected against transients in automotive
Undervoltage detection on pins V_CC, V_IO and VBAT
Thermally protected

Product Programs

EdgeLock^® Assurance

The TJA1153, part of the EdgeLock Assurance program, is designed to meet industry standards and follows NXP's security-by-design approach.

Buy/Parametrics

Part Show description	Order	CAD Model	Status	Package Type	Package Pitch (mm)	Recommended Orderable Part Number	MCU I/O Interface (V)	VIO Option Available	Low Power Modes	Data Rate [max] kbps	CAN Channels	Product Category	Supply Voltage [Min to Max] (V)	Data Rate [min] kbps	Voltage on bus pins [Min-Max] (V)	VESD IEC on bus pins (+/- kV)	VESD HBM on bus pins (+/- kV)	Junction Temperature (Max) (℃)	Protection	Wake-Up Pin	Min High Input Levels (V) [Vio]	Supported standards	SPLIT Pin	Thermal Resistance (Spec) (℃/W)	Product Application
TJA1153ATK			Active	HVSON14	0.65	TJA1153ATK/0Z	3.3, 5.0	Y	Sleep Mode, Standby Mode	5000.0	1	Secure CAN / High-Speed CAN / CAN FD	4.75 to 5.25	40.0	-58 to 58	0 to 0	0 to 0	150	TXD dominant timeout, overtemperature, undervoltage	Y	2.1	ISO-11898-2:2016, SAE J2284-1, SAE J2284-2, SAE J2284-3, SAE J2284-4, SAE J2284-5	N	50	Automotive, Industrial