Layerscape 2084A and 2044A

Layerscape 2084A and 2044A | NXP Semiconductors

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The LS2 family of processors delivers unprecedented performance and integration for tomorrow's smarter, more capable networks. The eight-core LS2084A and the four-core LS2044A multicore processors offer Arm^® Cortex^®- A72 cores with the advanced, high-performance datapath and network peripheral interfaces required for networking, telecom/datacom, wireless infrastructure, military, aerospace and automotive applications.

The next-generation datapath architecture, combined with a powerful software toolkit, provides a higher level of hardware abstraction and makes software development quick and simple.

This combination balances ease-of-use with high-performance processing in a Linux^® environment that is familiar to any software programmer. Customers can fully exploit the underlying hardware and easily adapt to network changes for real-time 'soft' control over the network.

Layerscape processors are part of NXP's EdgeVerse™ edge computing platform.

Data Sheet

Reference Manual

Product Details

Block Diagram

LS2084A Processor Block Diagram

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Features

Core Complex

Eight 64-bit Arm Cortex-A72 CPUs
- Up to 2 GHz,
- Clusters of two cores sharing 1 MB L2 cache
1 MB L3 platform cache
Two 64-bit DDR4 SDRAM memory controllers
- ECC and interleaving support,
- Up to 2.1 GT/s

Networking Elements

Wire Rate I/O processor, featuring:
- 8x 10 GbE
- 8x 1 GbE
- L2 switching on the Ethernet interface
- XAUI/XFI/KR and SGMII
- MACSec on up to four 1/10 GbE
2x SATA 3.0
4x PCIe Gen 3 controllers
SR-IOV support, Root Complex

Accelerators and Memory Control

20 Gb/s SEC crypto acceleration
10 Gb/s Pattern Matching Engine
20 Gb/s Data Compression Engine
4 PCIe controllers (Gen3) supporting 1x8, 4x4, 4x2, 4x1 lane configurations

Basic Peripherals and Interconnect

Support for hardware virtualization and partitioning enforcement
Implements trust architecture combined with TrustZone^®
- Service processor (SP) provides pre-boot initialization and secure-boot capabilities
2x USB 3.0 with PHY
Enhanced secure digital host controller
Serial peripheral interface (SPI) controller
Quad Serial peripheral interface (QSPI) controller
Four I²C controllers
Two DUARTs
Integrated flash controller (IFC 2.0) supporting NAND and NOR flash

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Design Resources

Design Files

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Layerscape 2084A and 2044A Multicore Processors

Product Details

Block Diagram

LS2084A Processor Block Diagram

Features

Core Complex

Networking Elements

Accelerators and Memory Control

Basic Peripherals and Interconnect

Related products

Applications

Automotive

Consumer

Industrial

Buy/Parametrics

Documentation

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Application Note (15)

Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces[AN5097]

Enabling 10GBase-KR on QorIQ Platforms Application Note[AN12750]

Chaining FlexTimers on Layerscape Devices[AN13608]

Ethernet Backplane Driver Support Application Note[AN12572]

Network subsystem troubleshooting on DPAA2 devices (illustrated with LX2160)[AN13329]

QorIQ LS2088A Family Design Checklist[AN4977]

PBL Configuration using QCVS Application Note[AN5260]

Optimizing Memory Copy Routines Application Note[AN12628]

General soldering Temperature Process Guidelines[AN3300]

AN11979, DPAA2 Ethernet Switch and Edge Virtual Bridge - Application Note[AN11979]

AN5199, Key Concepts for the Transition from DPAA1 to DPAA2 - Application Note[AN5199]

AN5125, Introduction to Device Trees - Application Note[AN5125]

SerDes Reference Clock Interfacing and HSSI Measurements Recommendations[AN4311]

DDR Interleaving for PowerQUICC and QorIQ Processors[AN3939]

Solder Joint Temperature and Package Peak Temperature[AN3298]

Data Sheet (1)

LS2084A/LS2044A Data Sheet[LS2084A]

Errata (1)

LX2084 Errata[LX2084-ERRATA-LINK]

Fact Sheet (1)

LAYERSCAPE LS2044A AND LS2084A COMMUNICATIONS PROCESSORS[LS2084AFS]

Reference Manual (2)

QorIQ LS2088A Reference Manual[LS2088ARM]

LS2088ASECRM, LS2088A Security (SEC) Reference Manual - Reference Manual[LS2088ASECRM]

Supporting Information (1)

FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP® Cryptographic Accelerators - White Paper[FSLNISTCAVP]

User Manual (1)

DPAA2 User Manual[DPAA2UM]

White Paper (1)

VIRTUAL AND SOFTWARE SOLUTIONS: THE BATTLE FOR ENTERPRISE NETWORK SUPREMACY[VIRTUAL-SOFTWARE-SOLUTIONS-WP]