Low-Power PowerQUICC® II Pro Processor with DDR2, PCI, 1 GB Ethernet, Security, USB | NXP Semiconductors

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Low-Power PowerQUICC® II Pro Processor with DDR2, PCI, 1 GB Ethernet, Security, USB

MPC8313E Not Recommended for New Designs

Rapid growth of personal and premium content has created a need for deploying more interactive multimedia services inside the home. The MPC8313E processor family enables feature-rich applications that enhance the digital home experience. The cost-effective MPC8313E communications processor family meets the requirements of several small office/home office (SOHO), printing, IP services and industrial control applications. It provides more CPU performance, additional functionality and faster interfaces while addressing important time to market, price, power consumption and board real estate requirements. The introduction of Gigabit Ethernet (SGMII), high-speed USB 2.0 and low-power management makes it stand out in the marketplace. For extremely precise clock synchronization for applications such as time-sensitive telecommunications services, industrial network switches, powerline networks and test/measurement devices, the MPC8313E features integrated IEEE® 1588 time synchronization, the leading-edge standard.

Block Diagram

NXP PowerQUICC MPC8313E Communications Processor Block Diagram

NXP<sup>&#174;</sup> PowerQUIICC MPC8313E Communications Processor Block Diagram
Get diagram PDF

Features

  • Core: e300c3, 2-IU, w/FPU, up to 400 MHz
  • L1 cache: 16 KB I/D
  • Memory controller: 16/32-bit DDR2-333
  • Local bus controller: 25b/8b dedicated or 25b/16b mux add/data, up to 66 MHz
  • PCI: one 32-bit up to 66 MHz wake-on-PME
  • Ethernet: two 10/100/1000 MACs, SGMII, 98145.452
  • 98145.452: one high-speed USB 2.0 host/device+HS PHY,
    wake-on-USB
  • Security: SEC 2.2 (MPC8313E only)
  • UART: dual
  • I²C: dual
  • Serial peripheral interface: one
  • Boot options: NOR, NAND
  • Internal controller: PIC
  • Mux/Dedicated GPIO: 10/16
  • DMA: four channels
  • Estimated core power: 1.2W
  • Power management: standby power <300 mW
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch

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N true 0 PSPMPC8313Een 36 Application Note Application Note t789 19 Application Note Software Application Note Software t783 3 Brochure Brochure t518 1 Data Sheet Data Sheet t520 1 Errata Errata t522 1 Fact Sheet Fact Sheet t523 2 Product Brief Product Brief t532 1 Reference Manual Reference Manual t877 3 Supporting Information Supporting Information t531 3 White Paper White Paper t530 2 en_US 4 1 1 English The MPC8313E processor family enables feature rich applications that enhance the digital home experience. The cost-effective MPC8313E communications processor family meets the requirements of several small office/home office (SOHO), printing, IP services and industrial control applications. The e300 core complex also includes 16 KB of L1 instruction and data caches and on-chip memory management units (MMUs). 1163535835404734846058 PSP 900.5 KB None None documents None 1163535835404734846058 /docs/en/fact-sheet/MPC8313PRPREFS.pdf 900452 /docs/en/fact-sheet/MPC8313PRPREFS.pdf MPC8313PRPREFS N 2006-11-15 MPC8313E PowerQUICC<sup>&#174;</sup> &#8482; II Pro Processor - Fact Sheet /docs/en/fact-sheet/MPC8313PRPREFS.pdf /docs/en/fact-sheet/MPC8313PRPREFS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 pdf en Jun 9, 2010 Fact Sheet t523 Fact Sheet Fact Sheet Y N MPC8313E PowerQUICC<sup>&#174;</sup> &#8482; II Pro Processor - Fact Sheet 2 3 English This reference manual defines the functionality of the MPC8313E. It is written from the perspective of the MPC8313E, which is the superset device, and unless otherwise noted, the information applies also to the MPC8313. 1163539134457705852596 PSP 9.8 MB None None documents None 1163539134457705852596 /docs/en/reference-manual/MPC8313ERM.pdf 9806645 /docs/en/reference-manual/MPC8313ERM.pdf MPC8313ERM N 2006-11-14 MPC8313E Reference Manual /docs/en/reference-manual/MPC8313ERM.pdf /docs/en/reference-manual/MPC8313ERM.pdf Reference Manual N Y 500633505221135046 2022-12-07 pdf en Aug 4, 2010 Reference Manual t877 Reference Manual Reference Manual Y N MPC8313E Reference Manual 3 0 English This document provides an overview of the MPC8313E PowerQUICC<sup>&#174;</sup> II Pro processor features, including a block diagram showing the major functional components. 1166473353896717253803 PSP 567.4 KB None None documents None 1166473353896717253803 /docs/en/product-brief/MPC8313EPB.pdf 567359 /docs/en/product-brief/MPC8313EPB.pdf MPC8313EPB N 2006-12-18 MPC8313E Product Brief /docs/en/product-brief/MPC8313EPB.pdf /docs/en/product-brief/MPC8313EPB.pdf Product Brief N Y 899114358132306053 2022-12-07 pdf en Dec 18, 2006 Product Brief t532 Product Brief Product Brief Y N MPC8313E Product Brief 4 4 English This document provides an overview of the MPC8313E PowerQUICC<sup>&#174;</sup>&#8482;II Pro processor features, including a block diagram showing the major functional components. 1181354468058712244517 PSP 881.0 KB None None documents None 1181354468058712244517 /docs/en/data-sheet/MPC8313EEC.pdf 881041 /docs/en/data-sheet/MPC8313EEC.pdf MPC8313EEC N N 2007-06-08 MPC8313E Data Sheet /docs/en/data-sheet/MPC8313EEC.pdf /docs/en/data-sheet/MPC8313EEC.pdf Data Sheet N Y 980000996212993340 2022-12-07 pdf N en Nov 8, 2011 Data Sheet t520 Data Sheet Data Sheet Y N MPC8313E Data Sheet false en_US en Reference Manual Reference Manual 2 5 4.1 English This addendum describes corrections to the e300 Power Architecture&#8482; Core Family Reference Manual, Revision 4. 1264006256879704515314 PSP 424.6 KB None None documents None 1264006256879704515314 /docs/en/reference-manual/e300CORERMAD.pdf 424614 /docs/en/reference-manual/e300CORERMAD.pdf E300CORERMAD documents N 2010-01-20 Errata to e300 Power Architecture&#8482; Core Family Reference Manual, Rev. 4 /docs/en/reference-manual/e300CORERMAD.pdf /docs/en/reference-manual/e300CORERMAD.pdf Reference Manual N 500633505221135046 2022-12-07 pdf en Jan 20, 2010 500633505221135046 Reference Manual Y N Errata to e300 Power Architecture&#8482; Core Family Reference Manual, Rev. 4 6 4 English Supports e300c1, e300c2, e300c3, e300c4. The primary objective of this reference manual is to describe the functionality of the microprocessors in the e300 core family, which are PowerPC &#8482; microprocessors built on Power Architecture &#8482; technology. The e300 designs are based on the MPC603e microprocessor. 1113346645199746873364 PSP 3.9 MB None None documents None 1113346645199746873364 /docs/en/reference-manual/e300coreRM.pdf 3862349 /docs/en/reference-manual/e300coreRM.pdf E300CORERM documents N 2005-04-12 e300 Power Architecture &#8482; Core Family - Reference Manual /docs/en/reference-manual/e300coreRM.pdf /docs/en/reference-manual/e300coreRM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf en Dec 12, 2007 500633505221135046 Reference Manual Y N e300 Power Architecture &#8482; Core Family - Reference Manual Application Note Application Note 19 7 0 Chinese Reviewing the troubleshoot microcontroller when there is a malfunction module. 1641302649210707506203zh PSP 303.0 KB None None documents None 1641302649210707506203 /docs/zh/application-note/AN13461.pdf 302971 /docs/zh/application-note/AN13461.pdf AN13461 documents N N 2022-01-04 AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note /docs/zh/application-note/AN13461.pdf /docs/zh/application-note/AN13461.pdf Application Note N 645036621402383989 2022-12-07 zh May 9, 2022 645036621402383989 Application Note Y N 恩智浦微控制器故障排除清单 0 English Reviewing the troubleshoot microcontroller when there is a malfunction module. 1641302649210707506203 PSP 303.0 KB None None documents None 1641302649210707506203 /docs/en/application-note/AN13461.pdf 302971 /docs/en/application-note/AN13461.pdf AN13461 documents N N 2022-01-04 AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note /docs/en/application-note/AN13461.pdf /docs/en/application-note/AN13461.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 30, 2021 645036621402383989 Application Note Y N AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note 8 3 English This document is a supplement to the SEC 2/3x reference device driver. 1224778148188710027580 PSP 1.1 MB Registration without Disclaimer None documents Extended 1224778148188710027580 /secured/assets/documents/en/application-note/AN3645.pdf 1147132 /secured/assets/documents/en/application-note/AN3645.pdf AN3645 documents Y N 2016-10-31 SEC 2/3x Descriptor Programmer’s Guide /webapp/Download?colCode=AN3645 /secured/assets/documents/en/application-note/AN3645.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Apr 28, 2017 645036621402383989 Application Note N SEC 2/3x Descriptor Programmer’s Guide 9 11 English AN2583: This application note provides programming guidelines for the PowerQUICC<sup>&#174;</sup> DDR-SDRAM memory controller and specifically JEDEC-compatible DDR1 SDRAM memories. 1070297961506735248621 PSP 333.2 KB None None documents None 1070297961506735248621 /docs/en/application-note/AN2583.pdf 333170 /docs/en/application-note/AN2583.pdf AN2583 documents N N 2003-12-01 AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note /docs/en/application-note/AN2583.pdf /docs/en/application-note/AN2583.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jul 29, 2014 645036621402383989 Application Note Y N AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note 10 3 English This design checklist describes the generally recommended connections for new designs based on the NXP MPC8313E and MPC8313 processors. The design checklist may also apply to future bus or footprint-compatible processors. It can also serve as a useful guide to debugging a newly-designed system, by highlighting those areas of a design that merit special attention during initial system startup. 1179210348737698729456 PSP 412.2 KB None None documents None 1179210348737698729456 /docs/en/application-note/AN3362.pdf 412233 /docs/en/application-note/AN3362.pdf AN3362 documents N N 2007-05-15 Design Checklist for PowerQUICC<sup>&#174;</sup> II Pro MPC8313E Processor /docs/en/application-note/AN3362.pdf /docs/en/application-note/AN3362.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Oct 31, 2011 645036621402383989 Application Note Y N Design Checklist for PowerQUICC<sup>&#174;</sup> II Pro MPC8313E Processor 11 0 English AN3830: This application note provides a practical guide to using Our CodeWarrior IDE to debug hardware. Focusing on PowerQUICC<sup>&#174;</sup> processors, this document covers many of the key features available in the IDE to assist in bring-up and troubleshooting of a new board. 1245429781973738421244 PSP 1.6 MB None None documents None 1245429781973738421244 /docs/en/application-note/AN3830.pdf 1576181 /docs/en/application-note/AN3830.pdf AN3830 documents N 2009-06-19 AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes /docs/en/application-note/AN3830.pdf /docs/en/application-note/AN3830.pdf Application Note N 645036621402383989 2022-12-07 pdf en Feb 1, 2011 645036621402383989 Application Note Y N AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes 12 0 English 1287581868481730872047 PSP 142.0 KB None None documents None 1287581868481730872047 /docs/en/application-note/AN3423.pdf 141965 /docs/en/application-note/AN3423.pdf AN3423 documents N 2016-10-31 Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors /docs/en/application-note/AN3423.pdf /docs/en/application-note/AN3423.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 6, 2010 645036621402383989 Application Note N Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors 13 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939 /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors 14 0 English AN4026SW.zip /secured/assets/documents/en/application-note-software/AN4026SW.zip /webapp/Download?colCode=AN4026SW&appType=license&docLang=en A common use of the QUICC Engine block is to establish an HDLC communication path over a TDM interface, such as a T1 or E1 link. This application note describes the various sub-blocks used in the QUICC Engine communications engine for this application, discusses how the sub-blocks interoperate with each other, describes how to initialize them for the HDLC communication path, and provides a software demonstration of HDLC mode via a TDM interface using on-chip loopback. 1260992898773711434436 PSP 718.0 KB None None documents None 1260992898773711434436 /docs/en/application-note/AN4026.pdf 718019 /docs/en/application-note/AN4026.pdf AN4026 documents N 2009-12-17 Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC /docs/en/application-note/AN4026.pdf /docs/en/application-note/AN4026.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 17, 2009 645036621402383989 Application Note N Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC 15 0 English High-level data link control (HDLC) is widely used in the telecommunications and networking industries. NXP&#8217;s PowerQUICC&#8482; communications processors have extensive support for HDLC protocol through the communications processor module (CPM) and QUICC Engine&#8482; technologies.&#13;&#10;&#13;&#10;This application note explains how NXP&#8217;s existing&#13;&#10;PowerQUICC communications processors use the CPM and QUICC Engine technologies to support the HDLC protocol and provides HDLC e 1258066893562722616236 PSP 496.6 KB None None documents None 1258066893562722616236 /docs/en/application-note/AN3966.pdf 496625 /docs/en/application-note/AN3966.pdf AN3966 documents N 2016-10-31 PowerQUICC™ HDLC Support and Example Code /docs/en/application-note/AN3966.pdf /docs/en/application-note/AN3966.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 10, 2009 645036621402383989 Application Note N PowerQUICC™ HDLC Support and Example Code 16 0 English The MPC8313E reference design board (RDB) is a system featuring the PowerQUICC&#8482; II Pro processor that includes a built-in security accelerator. The software board supported package (BSP) for this low-cost, high-performance system solution is available on the NXP website. The BSP enables the fastest possible time-to-market for development or integration of applications, including printer engines, broadband gateways, no-new-wires home adapters and access points, and home automation boxes. 1257227114355719715288 PSP 194.6 KB None None documents None 1257227114355719715288 /docs/en/application-note/AN3947.pdf 194617 /docs/en/application-note/AN3947.pdf AN3947 documents N 2009-11-02 How to Run the Latest Linux BSP on MPC8313ERDB Rev. Ax Boards /docs/en/application-note/AN3947.pdf /docs/en/application-note/AN3947.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 2, 2009 645036621402383989 Application Note Y N How to Run the Latest Linux BSP on MPC8313ERDB Rev. Ax Boards 17 1 English This document explores the migration from silicon revision 1.0 to 2.0 with respect to software, hardware, internal module revision, and chip pin assignment, and serves as a relevant guide for both software and hardware developers. 1203630742938707945727 PSP 528.2 KB None None documents None 1203630742938707945727 /docs/en/application-note/AN3545.pdf 528234 /docs/en/application-note/AN3545.pdf AN3545 documents N 2008-02-21 Migration from MPC8313E Revision 1.0 to Revision 2.0 /docs/en/application-note/AN3545.pdf /docs/en/application-note/AN3545.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 23, 2008 645036621402383989 Application Note Y N Migration from MPC8313E Revision 1.0 to Revision 2.0 18 5.0 English This document expands on the description of the double data rate (DDR2) memory controller programmable registers described in the reference manuals for PowerQUICC processors. The corresponding material in the reference manual defines the function of each field in the programmable registers. This application note focuses when and why to select certain configurations of the bits and fields in the DDR2 registers to achieve efficient DDR programming. 1176147669904707686124 PSP 535.3 KB None None documents None 1176147669904707686124 /docs/en/application-note/AN3369.pdf 535277 /docs/en/application-note/AN3369.pdf AN3369 documents N 2007-04-09 PowerQUICC<sup>&#174;</sup> DDR2 SDRAM Controller Register Setting Considerations /docs/en/application-note/AN3369.pdf /docs/en/application-note/AN3369.pdf Application Note N 645036621402383989 2022-12-07 pdf en Sep 11, 2008 645036621402383989 Application Note Y N PowerQUICC<sup>&#174;</sup> DDR2 SDRAM Controller Register Setting Considerations 19 0 English This application note provides an overview and specific strategies for cache coherency and potential performance impacts in the PowerQUICC<sup>&#174;</sup> II Pro and PowerQUICC III families. It focuses on data coherency and potential system issues, as well as some concerns associated with having multiple DMA devices. It also discusses the specific steps and interdependencies required to implement hardware enforced cache coherency. 1198270786976715604383 PSP 547.7 KB None None documents None 1198270786976715604383 /docs/en/application-note/AN3544.pdf 547694 /docs/en/application-note/AN3544.pdf AN3544 documents N 2016-10-31 PowerQUICC™ Data Cache Coherency /docs/en/application-note/AN3544.pdf /docs/en/application-note/AN3544.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 21, 2007 645036621402383989 Application Note N PowerQUICC™ Data Cache Coherency 20 0 English This application note explains how to program one of the eLBC&#8217;s user-programmable machines (UPMs) to control an SDRAM memory device. 1194558645992741221612 PSP 574.8 KB None None documents None 1194558645992741221612 /docs/en/application-note/AN3533.pdf 574761 /docs/en/application-note/AN3533.pdf AN3533 documents N 2007-11-08 Programming the User-Programmable Machine (UPM) for SDRAM Memory Devices /docs/en/application-note/AN3533.pdf /docs/en/application-note/AN3533.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 8, 2007 645036621402383989 Application Note Y N Programming the User-Programmable Machine (UPM) for SDRAM Memory Devices 21 Rev 0 English This application note provides a brief overview of the FCM operation and describes the implementation of a bootloader using u-boot [1] for the MPC8313 device with a small-page NAND device (Samsung K9F5608U0D and Micron MT29F2G08AACWP). 1183018399022715874213 PSP 125.4 KB None None documents None 1183018399022715874213 /docs/en/application-note/AN3201.pdf 125367 /docs/en/application-note/AN3201.pdf AN3201 documents N 2007-06-28 Using U-boot to Boot From a NAND Flash Memory Device for MPC8313E /docs/en/application-note/AN3201.pdf /docs/en/application-note/AN3201.pdf Application Note N 645036621402383989 2022-12-07 pdf en Jun 28, 2007 645036621402383989 Application Note Y N Using U-boot to Boot From a NAND Flash Memory Device for MPC8313E 22 Rev 0 English The performance monitor is a module on PowerQUICC&#8482; MPC83xx processors that counts predefined events and processor clocks associated with operations such as cache misses, mispredicted branches, and so on. The count of such events can be used to trigger a performance monitor interrupt. The performance monitor helps to identify system bottlenecks and can improve system performance by monitoring the software execution and recording the algorithms for more efficiency. This profiling tool must be used with 1179210664491698304323 PSP 461.8 KB None None documents None 1179210664491698304323 /docs/en/application-note/AN3359.pdf 461802 /docs/en/application-note/AN3359.pdf AN3359 documents N 2007-05-15 Performance Monitor on PowerQUICC<sup>&#174;</sup> II Pro Processors /docs/en/application-note/AN3359.pdf /docs/en/application-note/AN3359.pdf Application Note N 645036621402383989 2022-12-07 pdf en May 15, 2007 645036621402383989 Application Note Y N Performance Monitor on PowerQUICC<sup>&#174;</sup> II Pro Processors 23 Rev 0 English This application note describes the implementation of the Linux&#174; power management on the PowerQUICC&#8482; MPC8313E processor. The MPC8313E has features to minimize power consumption at several levels. Dynamic power management locally minimizes power consumption when a block is idle. Many blocks in the MPC8313E can dynamically turn off clocks when sections of the block are idle. This feature is always enabled and occurs automatically. Clocks to the individual blocks can be shut down when they are not n 1179144007209710374933 PSP 479.6 KB None None documents None 1179144007209710374933 /docs/en/application-note/AN3371.pdf 479642 /docs/en/application-note/AN3371.pdf AN3371 documents N 2007-05-15 Power Management in Linux for the PowerQUICC<sup>&#174;</sup> MPC8313E /docs/en/application-note/AN3371.pdf /docs/en/application-note/AN3371.pdf Application Note N 645036621402383989 2022-12-07 pdf en May 15, 2007 645036621402383989 Application Note Y N Power Management in Linux for the PowerQUICC<sup>&#174;</sup> MPC8313E 24 Rev 0 English The serial gigabit media-independent interface (SGMII) is the interface with the lowest pin count available for connecting compatible MACs and PHYs. It consists of pairs of Txdata, Rxdata, and Rx Ref Clk data pins. It can also be used as a serial communication bus between the PowerQUICC&#8482; MPC8313E and other peripherals such as through a backplane. A key advantage of SGMII is that it can operate at multiple speeds of 10/100/1000 Mbps. &#13;&#10;This application note describes how to configure SGMII mode 1179210017991720932563 PSP 478.0 KB None None documents None 1179210017991720932563 /docs/en/application-note/AN3354.pdf 478025 /docs/en/application-note/AN3354.pdf AN3354 documents N 2007-05-15 Configuring SGMII Ethernet on the PowerQUICC<sup>&#174;</sup> MPC8313E Processor /docs/en/application-note/AN3354.pdf /docs/en/application-note/AN3354.pdf Application Note N 645036621402383989 2022-12-07 pdf en May 15, 2007 645036621402383989 Application Note Y N Configuring SGMII Ethernet on the PowerQUICC<sup>&#174;</sup> MPC8313E Processor 25 2 English These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. 1128961595061725581551 PSP 619.7 KB None None documents None 1128961595061725581551 /docs/en/application-note/AN2910.pdf 619650 /docs/en/application-note/AN2910.pdf AN2910 documents N 2016-10-31 Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf /docs/en/application-note/AN2910.pdf Application Note N 645036621402383989 2022-12-07 pdf en Mar 27, 2007 645036621402383989 Application Note N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces Application Note Software Application Note Software 3 26 0 English 1258066894053701788655 PSP 330.9 KB Registration With Click-Thru Software Licensing Agreement 1395958162559706127527 documents Extended 1258066894053701788655 /secured/assets/documents/en/application-note-software/AN3966SW.zip 330857 /secured/assets/documents/en/application-note-software/AN3966SW.zip AN3966SW documents Y N 2016-10-31 Software to accompany application note AN3966 /webapp/Download?colCode=AN3966SW&appType=license /secured/assets/documents/en/application-note-software/AN3966SW.zip Application Note Software N 789425793691620447 2022-12-07 zip Y en Nov 10, 2009 789425793691620447 Application Note Software N Software to accompany application note AN3966 27 0 English This application note addresses a common challenge encountered during circuit board testing with some of the newer NXP microprocessors. It is common practice for board testing houses to test for shorts on the power rails by measuring the resistance from a power rail to the ground rail. In older technologies, this is a reasonable approach. However, this application note explains why this approach can be problematic when used with devices in newer technologies. 1181767584945705509512 PSP 163.7 KB None None documents None 1181767584945705509512 /docs/en/application-note-software/AN3372.pdf 163681 /docs/en/application-note-software/AN3372.pdf AN3372 documents N 2016-10-31 Challenges in Testing for Power Rail Shorts with New Technologies /docs/en/application-note-software/AN3372.pdf /docs/en/application-note-software/AN3372.pdf Application Note Software N 789425793691620447 2022-12-07 pdf en Jun 13, 2007 789425793691620447 Application Note Software N Challenges in Testing for Power Rail Shorts with New Technologies 28 0 English This application note describes the steps required to initialize an MPC83xx device operating as a PCI agent. It compares initialization from the PCI host with initialization from the on-board e300 processor. It starts with an overview of the initialization process and then discusses key architectural considerations, hardware reset considerations, minimum initialization required to run software, and system implications. The procedure in this application note was performed with the MPC834x family, but it appl 1175891986109734102869 PSP 460.2 KB None None documents None 1175891986109734102869 /docs/en/application-note-software/AN3373.pdf 460203 /docs/en/application-note-software/AN3373.pdf AN3373 documents N 2007-04-06 PowerQUICC<sup>&#174;</sup> II Pro (MPC83xx) PCI Agent Initialization /docs/en/application-note-software/AN3373.pdf /docs/en/application-note-software/AN3373.pdf Application Note Software N 789425793691620447 2022-12-07 pdf en Apr 6, 2007 789425793691620447 Application Note Software D N PowerQUICC<sup>&#174;</sup> II Pro (MPC83xx) PCI Agent Initialization Brochure Brochure 1 29 1 English NXP, known for its&#13;&#10;design and integration capabilities, designed&#13;&#10;the versatile MPC8313E, MPC8315E and&#13;&#10;MPC8314E PowerQUICC<sup>&#174;</sup>&#174; processors to&#13;&#10;integrate hardware for Ethernet and serial&#13;&#10;communications, memory interfaces, USB&#13;&#10;ports, security and other popular inputs&#13;&#10;and outputs in a ubiquitous architecture&#13;&#10;engineered to serve several markets equally&#13;&#10;well. 1208376113735717128975 PSP 828.2 KB None None documents None 1208376113735717128975 /docs/en/brochure/MPC831x_Brochure.pdf 828236 /docs/en/brochure/MPC831x_Brochure.pdf MPC831X_BROCHURE documents N 2008-04-16 MPC831x /docs/en/brochure/MPC831x_Brochure.pdf /docs/en/brochure/MPC831x_Brochure.pdf Brochure N 712453003803778552 2022-12-07 pdf en Apr 16, 2008 712453003803778552 Brochure Y N MPC831x Errata Errata 1 30 7 English This document describes all known silicon errata for the MPC8313E PowerQUICC<sup>&#174;</sup> II Pro integrated host processor, silicon revision 1.0 and 2.x. 1181338408443723018244 PSP 674.6 KB None None documents None 1181338408443723018244 /docs/en/errata/MPC8313ECE.pdf 674576 /docs/en/errata/MPC8313ECE.pdf MPC8313ECE documents N N 2007-06-08 MPC8313E Chip Errata - Chip Errata /docs/en/errata/MPC8313ECE.pdf /docs/en/errata/MPC8313ECE.pdf Errata N 155452329886410597 2022-12-07 pdf N en Jun 23, 2014 155452329886410597 Errata Y N MPC8313E Chip Errata - Chip Errata Fact Sheet Fact Sheet 1 31 4 English QUICC Engine<sup>&#174;</sup>TM and Enhanced Triple Speed Ethernet Controller (eTSEC) are the first NXP communications interfaces to optimize IEEE 1588 Precision Time Protocol (PTP) in hardware. 1153163047046710587034 PSP 216.3 KB None None documents None 1153163047046710587034 /docs/en/fact-sheet/PQIEEE1588FS.pdf 216278 /docs/en/fact-sheet/PQIEEE1588FS.pdf PQIEEE1588FS documents N N 2016-10-31 PowerQUICC Integrates IEEE 1588 Time Synchronization /docs/en/fact-sheet/PQIEEE1588FS.pdf /docs/en/fact-sheet/PQIEEE1588FS.pdf Fact Sheet N 736675474163315314 2022-12-07 pdf N en Feb 14, 2008 736675474163315314 Fact Sheet Y N PowerQUICC Integrates IEEE 1588 Time Synchronization Supporting Information Supporting Information 3 32 1.9 English FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. 1368836090577704535160 PSP 303.5 KB None None documents None 1368836090577704535160 /docs/en/supporting-information/FSLNISTCAVP.pdf 303546 /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP documents N N 2016-11-09 FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf /docs/en/supporting-information/FSLNISTCAVP.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 28, 2016 371282830530968666 Supporting Information Y N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 33 0 English 1292347737662695465152 PSP 12.6 KB None None documents None 1292347737662695465152 /docs/en/supporting-information/MPC8311_8313PECI.pdf 12582 /docs/en/supporting-information/MPC8311_8313PECI.pdf MPC8311_8313PECI documents N 2010-12-14 MPC8311_8313 Customer Export Control Info /docs/en/supporting-information/MPC8311_8313PECI.pdf /docs/en/supporting-information/MPC8311_8313PECI.pdf Supporting Information N 371282830530968666 2023-06-19 pdf en Dec 10, 2010 371282830530968666 Supporting Information Y N MPC8311_8313 Customer Export Control Info 34 1 English MPC8313 Customer Export Control Information Document 1232680180782714601297 PSP 191.5 KB None None documents None 1232680180782714601297 /docs/en/supporting-information/MPC8311E_8313EPECI.pdf 191492 /docs/en/supporting-information/MPC8311E_8313EPECI.pdf MPC8311E_8313EPECI documents N N 2016-10-31 MPC8313 Customer Export Control Information /docs/en/supporting-information/MPC8311E_8313EPECI.pdf /docs/en/supporting-information/MPC8311E_8313EPECI.pdf Supporting Information N 371282830530968666 2023-06-19 pdf N en Jan 19, 2009 371282830530968666 Supporting Information Y N MPC8313 Customer Export Control Information White Paper White Paper 2 35 3 English Network security protocols and applications use a variety of cryptographic algorithms to achieve these high-level goals. Because cryptography is computationally intensive, hardware acceleration is highly desirable when cryptographic algorithms are frequent system functions. 1227561595497709456436 PSP 580.1 KB Registration without Disclaimer None documents Extended 1227561595497709456436 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf 580121 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf CRYPTOWP documents Y N 2016-10-31 Understanding Cryptographic Performance /webapp/Download?colCode=CRYPTOWP /secured/assets/documents/en/white-paper/CRYPTOWP.pdf White Paper N 918633085541740938 2022-12-07 pdf Y en Aug 15, 2008 918633085541740938 White Paper Y N Understanding Cryptographic Performance 36 0 English The focus of this white paper is to provide the end user with high level design considerations and/or trade-offs associated with migrating from SDRAM to DDR SDRAM-based designs. 1208376896761708228520 PSP 735.3 KB None None documents None 1208376896761708228520 /docs/en/white-paper/DDRSDRAMWP.pdf 735286 /docs/en/white-paper/DDRSDRAMWP.pdf DDRSDRAMWP documents N N 2016-10-31 Comparison of DDRx and SDRAM /docs/en/white-paper/DDRSDRAMWP.pdf /docs/en/white-paper/DDRSDRAMWP.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Apr 16, 2008 918633085541740938 White Paper Y N Comparison of DDRx and SDRAM false 0 MPC8313E downloads en true 1 Y PSP Application Note 19 /docs/en/application-note/AN13461.pdf 2022-01-04 1641302649210707506203 PSP 7 Nov 30, 2021 Application Note Reviewing the troubleshoot microcontroller when there is a malfunction module. None /docs/en/application-note/AN13461.pdf English documents 302971 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN13461.pdf AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note /docs/en/application-note/AN13461.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note 303.0 KB AN13461 N 1641302649210707506203 /secured/assets/documents/en/application-note/AN3645.pdf 2016-10-31 1224778148188710027580 PSP 8 Apr 28, 2017 Application Note This document is a supplement to the SEC 2/3x reference device driver. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3645.pdf English documents 1147132 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3645 SEC 2/3x Descriptor Programmer’s Guide /secured/assets/documents/en/application-note/AN3645.pdf documents 645036621402383989 Application Note N en Extended pdf 3 Y N SEC 2/3x Descriptor Programmer’s Guide 1.1 MB AN3645 N 1224778148188710027580 /docs/en/application-note/AN2583.pdf 2003-12-01 1070297961506735248621 PSP 9 Jul 29, 2014 Application Note AN2583: This application note provides programming guidelines for the PowerQUICC<sup>&#174;</sup> DDR-SDRAM memory controller and specifically JEDEC-compatible DDR1 SDRAM memories. None /docs/en/application-note/AN2583.pdf English documents 333170 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN2583.pdf AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note /docs/en/application-note/AN2583.pdf documents 645036621402383989 Application Note N en None Y pdf 11 N N AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note 333.2 KB AN2583 N 1070297961506735248621 /docs/en/application-note/AN3362.pdf 2007-05-15 1179210348737698729456 PSP 10 Oct 31, 2011 Application Note This design checklist describes the generally recommended connections for new designs based on the NXP MPC8313E and MPC8313 processors. The design checklist may also apply to future bus or footprint-compatible processors. It can also serve as a useful guide to debugging a newly-designed system, by highlighting those areas of a design that merit special attention during initial system startup. None /docs/en/application-note/AN3362.pdf English documents 412233 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3362.pdf Design Checklist for PowerQUICC<sup>&#174;</sup> II Pro MPC8313E Processor /docs/en/application-note/AN3362.pdf documents 645036621402383989 Application Note N en None Y pdf 3 N N Design Checklist for PowerQUICC<sup>&#174;</sup> II Pro MPC8313E Processor 412.2 KB AN3362 N 1179210348737698729456 /docs/en/application-note/AN3830.pdf 2009-06-19 1245429781973738421244 PSP 11 Feb 1, 2011 Application Note AN3830: This application note provides a practical guide to using Our CodeWarrior IDE to debug hardware. Focusing on PowerQUICC<sup>&#174;</sup> processors, this document covers many of the key features available in the IDE to assist in bring-up and troubleshooting of a new board. None /docs/en/application-note/AN3830.pdf English documents 1576181 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3830.pdf AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes /docs/en/application-note/AN3830.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes 1.6 MB AN3830 N 1245429781973738421244 /docs/en/application-note/AN3423.pdf 2016-10-31 1287581868481730872047 PSP 12 Oct 6, 2010 Application Note None /docs/en/application-note/AN3423.pdf English documents 141965 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3423.pdf Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors /docs/en/application-note/AN3423.pdf documents 645036621402383989 Application Note N en None pdf 0 N Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors 142.0 KB AN3423 N 1287581868481730872047 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 13 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939 DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 /docs/en/application-note/AN4026.pdf 2009-12-17 1260992898773711434436 PSP 14 Dec 17, 2009 Application Note A common use of the QUICC Engine block is to establish an HDLC communication path over a TDM interface, such as a T1 or E1 link. This application note describes the various sub-blocks used in the QUICC Engine communications engine for this application, discusses how the sub-blocks interoperate with each other, describes how to initialize them for the HDLC communication path, and provides a software demonstration of HDLC mode via a TDM interface using on-chip loopback. None /docs/en/application-note/AN4026.pdf English documents 718019 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4026.pdf Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC /docs/en/application-note/AN4026.pdf documents 645036621402383989 Application Note N en None pdf 0 N Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC 718.0 KB AN4026 N 1260992898773711434436 /docs/en/application-note/AN3966.pdf 2016-10-31 1258066893562722616236 PSP 15 Nov 10, 2009 Application Note High-level data link control (HDLC) is widely used in the telecommunications and networking industries. NXP&#8217;s PowerQUICC&#8482; communications processors have extensive support for HDLC protocol through the communications processor module (CPM) and QUICC Engine&#8482; technologies.&#13;&#10;&#13;&#10;This application note explains how NXP&#8217;s existing&#13;&#10;PowerQUICC communications processors use the CPM and QUICC Engine technologies to support the HDLC protocol and provides HDLC e None /docs/en/application-note/AN3966.pdf English documents 496625 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3966.pdf PowerQUICC™ HDLC Support and Example Code /docs/en/application-note/AN3966.pdf documents 645036621402383989 Application Note N en None pdf 0 N PowerQUICC™ HDLC Support and Example Code 496.6 KB AN3966 N 1258066893562722616236 /docs/en/application-note/AN3947.pdf 2009-11-02 1257227114355719715288 PSP 16 Nov 2, 2009 Application Note The MPC8313E reference design board (RDB) is a system featuring the PowerQUICC&#8482; II Pro processor that includes a built-in security accelerator. The software board supported package (BSP) for this low-cost, high-performance system solution is available on the NXP website. The BSP enables the fastest possible time-to-market for development or integration of applications, including printer engines, broadband gateways, no-new-wires home adapters and access points, and home automation boxes. None /docs/en/application-note/AN3947.pdf English documents 194617 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3947.pdf How to Run the Latest Linux BSP on MPC8313ERDB Rev. Ax Boards /docs/en/application-note/AN3947.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N How to Run the Latest Linux BSP on MPC8313ERDB Rev. Ax Boards 194.6 KB AN3947 N 1257227114355719715288 /docs/en/application-note/AN3545.pdf 2008-02-21 1203630742938707945727 PSP 17 Oct 23, 2008 Application Note This document explores the migration from silicon revision 1.0 to 2.0 with respect to software, hardware, internal module revision, and chip pin assignment, and serves as a relevant guide for both software and hardware developers. None /docs/en/application-note/AN3545.pdf English documents 528234 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3545.pdf Migration from MPC8313E Revision 1.0 to Revision 2.0 /docs/en/application-note/AN3545.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N Migration from MPC8313E Revision 1.0 to Revision 2.0 528.2 KB AN3545 N 1203630742938707945727 /docs/en/application-note/AN3369.pdf 2007-04-09 1176147669904707686124 PSP 18 Sep 11, 2008 Application Note This document expands on the description of the double data rate (DDR2) memory controller programmable registers described in the reference manuals for PowerQUICC processors. The corresponding material in the reference manual defines the function of each field in the programmable registers. This application note focuses when and why to select certain configurations of the bits and fields in the DDR2 registers to achieve efficient DDR programming. None /docs/en/application-note/AN3369.pdf English documents 535277 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3369.pdf PowerQUICC<sup>&#174;</sup> DDR2 SDRAM Controller Register Setting Considerations /docs/en/application-note/AN3369.pdf documents 645036621402383989 Application Note N en None Y pdf 5.0 N PowerQUICC<sup>&#174;</sup> DDR2 SDRAM Controller Register Setting Considerations 535.3 KB AN3369 N 1176147669904707686124 /docs/en/application-note/AN3544.pdf 2016-10-31 1198270786976715604383 PSP 19 Dec 21, 2007 Application Note This application note provides an overview and specific strategies for cache coherency and potential performance impacts in the PowerQUICC<sup>&#174;</sup> II Pro and PowerQUICC III families. It focuses on data coherency and potential system issues, as well as some concerns associated with having multiple DMA devices. It also discusses the specific steps and interdependencies required to implement hardware enforced cache coherency. None /docs/en/application-note/AN3544.pdf English documents 547694 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3544.pdf PowerQUICC™ Data Cache Coherency /docs/en/application-note/AN3544.pdf documents 645036621402383989 Application Note N en None pdf 0 N PowerQUICC™ Data Cache Coherency 547.7 KB AN3544 N 1198270786976715604383 /docs/en/application-note/AN3533.pdf 2007-11-08 1194558645992741221612 PSP 20 Nov 8, 2007 Application Note This application note explains how to program one of the eLBC&#8217;s user-programmable machines (UPMs) to control an SDRAM memory device. None /docs/en/application-note/AN3533.pdf English documents 574761 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3533.pdf Programming the User-Programmable Machine (UPM) for SDRAM Memory Devices /docs/en/application-note/AN3533.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N Programming the User-Programmable Machine (UPM) for SDRAM Memory Devices 574.8 KB AN3533 N 1194558645992741221612 /docs/en/application-note/AN3201.pdf 2007-06-28 1183018399022715874213 PSP 21 Jun 28, 2007 Application Note This application note provides a brief overview of the FCM operation and describes the implementation of a bootloader using u-boot [1] for the MPC8313 device with a small-page NAND device (Samsung K9F5608U0D and Micron MT29F2G08AACWP). None /docs/en/application-note/AN3201.pdf English documents 125367 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3201.pdf Using U-boot to Boot From a NAND Flash Memory Device for MPC8313E /docs/en/application-note/AN3201.pdf documents 645036621402383989 Application Note N en None Y pdf Rev 0 N Using U-boot to Boot From a NAND Flash Memory Device for MPC8313E 125.4 KB AN3201 N 1183018399022715874213 /docs/en/application-note/AN3359.pdf 2007-05-15 1179210664491698304323 PSP 22 May 15, 2007 Application Note The performance monitor is a module on PowerQUICC&#8482; MPC83xx processors that counts predefined events and processor clocks associated with operations such as cache misses, mispredicted branches, and so on. The count of such events can be used to trigger a performance monitor interrupt. The performance monitor helps to identify system bottlenecks and can improve system performance by monitoring the software execution and recording the algorithms for more efficiency. This profiling tool must be used with None /docs/en/application-note/AN3359.pdf English documents 461802 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3359.pdf Performance Monitor on PowerQUICC<sup>&#174;</sup> II Pro Processors /docs/en/application-note/AN3359.pdf documents 645036621402383989 Application Note N en None Y pdf Rev 0 N Performance Monitor on PowerQUICC<sup>&#174;</sup> II Pro Processors 461.8 KB AN3359 N 1179210664491698304323 /docs/en/application-note/AN3371.pdf 2007-05-15 1179144007209710374933 PSP 23 May 15, 2007 Application Note This application note describes the implementation of the Linux&#174; power management on the PowerQUICC&#8482; MPC8313E processor. The MPC8313E has features to minimize power consumption at several levels. Dynamic power management locally minimizes power consumption when a block is idle. Many blocks in the MPC8313E can dynamically turn off clocks when sections of the block are idle. This feature is always enabled and occurs automatically. Clocks to the individual blocks can be shut down when they are not n None /docs/en/application-note/AN3371.pdf English documents 479642 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3371.pdf Power Management in Linux for the PowerQUICC<sup>&#174;</sup> MPC8313E /docs/en/application-note/AN3371.pdf documents 645036621402383989 Application Note N en None Y pdf Rev 0 N Power Management in Linux for the PowerQUICC<sup>&#174;</sup> MPC8313E 479.6 KB AN3371 N 1179144007209710374933 /docs/en/application-note/AN3354.pdf 2007-05-15 1179210017991720932563 PSP 24 May 15, 2007 Application Note The serial gigabit media-independent interface (SGMII) is the interface with the lowest pin count available for connecting compatible MACs and PHYs. It consists of pairs of Txdata, Rxdata, and Rx Ref Clk data pins. It can also be used as a serial communication bus between the PowerQUICC&#8482; MPC8313E and other peripherals such as through a backplane. A key advantage of SGMII is that it can operate at multiple speeds of 10/100/1000 Mbps. &#13;&#10;This application note describes how to configure SGMII mode None /docs/en/application-note/AN3354.pdf English documents 478025 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3354.pdf Configuring SGMII Ethernet on the PowerQUICC<sup>&#174;</sup> MPC8313E Processor /docs/en/application-note/AN3354.pdf documents 645036621402383989 Application Note N en None Y pdf Rev 0 N Configuring SGMII Ethernet on the PowerQUICC<sup>&#174;</sup> MPC8313E Processor 478.0 KB AN3354 N 1179210017991720932563 /docs/en/application-note/AN2910.pdf 2016-10-31 1128961595061725581551 PSP 25 Mar 27, 2007 Application Note These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. None /docs/en/application-note/AN2910.pdf English documents 619650 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2910.pdf Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf documents 645036621402383989 Application Note N en None pdf 2 N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces 619.7 KB AN2910 N 1128961595061725581551 Application Note Software 3 /secured/assets/documents/en/application-note-software/AN3966SW.zip 2016-10-31 1258066894053701788655 PSP 26 Nov 10, 2009 Application Note Software Registration With Click-Thru Software Licensing Agreement /secured/assets/documents/en/application-note-software/AN3966SW.zip English documents 330857 1395958162559706127527 789425793691620447 2022-12-07 Y /webapp/Download?colCode=AN3966SW&appType=license Software to accompany application note AN3966 /secured/assets/documents/en/application-note-software/AN3966SW.zip documents 789425793691620447 Application Note Software N en Extended zip 0 Y N Software to accompany application note AN3966 330.9 KB AN3966SW N 1258066894053701788655 /docs/en/application-note-software/AN3372.pdf 2016-10-31 1181767584945705509512 PSP 27 Jun 13, 2007 Application Note Software This application note addresses a common challenge encountered during circuit board testing with some of the newer NXP microprocessors. It is common practice for board testing houses to test for shorts on the power rails by measuring the resistance from a power rail to the ground rail. In older technologies, this is a reasonable approach. However, this application note explains why this approach can be problematic when used with devices in newer technologies. None /docs/en/application-note-software/AN3372.pdf English documents 163681 None 789425793691620447 2022-12-07 /docs/en/application-note-software/AN3372.pdf Challenges in Testing for Power Rail Shorts with New Technologies /docs/en/application-note-software/AN3372.pdf documents 789425793691620447 Application Note Software N en None pdf 0 N Challenges in Testing for Power Rail Shorts with New Technologies 163.7 KB AN3372 N 1181767584945705509512 /docs/en/application-note-software/AN3373.pdf 2007-04-06 1175891986109734102869 PSP 28 Apr 6, 2007 Application Note Software This application note describes the steps required to initialize an MPC83xx device operating as a PCI agent. It compares initialization from the PCI host with initialization from the on-board e300 processor. It starts with an overview of the initialization process and then discusses key architectural considerations, hardware reset considerations, minimum initialization required to run software, and system implications. The procedure in this application note was performed with the MPC834x family, but it appl None /docs/en/application-note-software/AN3373.pdf English documents 460203 None 789425793691620447 2022-12-07 /docs/en/application-note-software/AN3373.pdf PowerQUICC<sup>&#174;</sup> II Pro (MPC83xx) PCI Agent Initialization /docs/en/application-note-software/AN3373.pdf documents 789425793691620447 Application Note Software N en None D pdf 0 N PowerQUICC<sup>&#174;</sup> II Pro (MPC83xx) PCI Agent Initialization 460.2 KB AN3373 N 1175891986109734102869 Brochure 1 /docs/en/brochure/MPC831x_Brochure.pdf 2008-04-16 1208376113735717128975 PSP 29 Apr 16, 2008 Brochure NXP, known for its&#13;&#10;design and integration capabilities, designed&#13;&#10;the versatile MPC8313E, MPC8315E and&#13;&#10;MPC8314E PowerQUICC<sup>&#174;</sup>&#174; processors to&#13;&#10;integrate hardware for Ethernet and serial&#13;&#10;communications, memory interfaces, USB&#13;&#10;ports, security and other popular inputs&#13;&#10;and outputs in a ubiquitous architecture&#13;&#10;engineered to serve several markets equally&#13;&#10;well. None /docs/en/brochure/MPC831x_Brochure.pdf English documents 828236 None 712453003803778552 2022-12-07 /docs/en/brochure/MPC831x_Brochure.pdf MPC831x /docs/en/brochure/MPC831x_Brochure.pdf documents 712453003803778552 Brochure N en None Y pdf 1 N MPC831x 828.2 KB MPC831X_BROCHURE N 1208376113735717128975 Data Sheet 1 /docs/en/data-sheet/MPC8313EEC.pdf 2007-06-08 1181354468058712244517 PSP 4 Nov 8, 2011 Data Sheet Data Sheet This document provides an overview of the MPC8313E PowerQUICC<sup>&#174;</sup>&#8482;II Pro processor features, including a block diagram showing the major functional components. None /docs/en/data-sheet/MPC8313EEC.pdf English 881041 None Data Sheet 2022-12-07 N /docs/en/data-sheet/MPC8313EEC.pdf MPC8313E Data Sheet /docs/en/data-sheet/MPC8313EEC.pdf documents 980000996212993340 Data Sheet N Y en None Y t520 pdf 4 N N MPC8313E Data Sheet 881.0 KB MPC8313EEC N 1181354468058712244517 Errata 1 /docs/en/errata/MPC8313ECE.pdf 2007-06-08 1181338408443723018244 PSP 30 Jun 23, 2014 Errata This document describes all known silicon errata for the MPC8313E PowerQUICC<sup>&#174;</sup> II Pro integrated host processor, silicon revision 1.0 and 2.x. None /docs/en/errata/MPC8313ECE.pdf English documents 674576 None 155452329886410597 2022-12-07 N /docs/en/errata/MPC8313ECE.pdf MPC8313E Chip Errata - Chip Errata /docs/en/errata/MPC8313ECE.pdf documents 155452329886410597 Errata N en None Y pdf 7 N N MPC8313E Chip Errata - Chip Errata 674.6 KB MPC8313ECE N 1181338408443723018244 Fact Sheet 2 /docs/en/fact-sheet/PQIEEE1588FS.pdf 2016-10-31 1153163047046710587034 PSP 31 Feb 14, 2008 Fact Sheet QUICC Engine<sup>&#174;</sup>TM and Enhanced Triple Speed Ethernet Controller (eTSEC) are the first NXP communications interfaces to optimize IEEE 1588 Precision Time Protocol (PTP) in hardware. None /docs/en/fact-sheet/PQIEEE1588FS.pdf English documents 216278 None 736675474163315314 2022-12-07 N /docs/en/fact-sheet/PQIEEE1588FS.pdf PowerQUICC Integrates IEEE 1588 Time Synchronization /docs/en/fact-sheet/PQIEEE1588FS.pdf documents 736675474163315314 Fact Sheet N en None Y pdf 4 N N PowerQUICC Integrates IEEE 1588 Time Synchronization 216.3 KB PQIEEE1588FS N 1153163047046710587034 /docs/en/fact-sheet/MPC8313PRPREFS.pdf 2006-11-15 1163535835404734846058 PSP 1 Jun 9, 2010 Fact Sheet Fact Sheet The MPC8313E processor family enables feature rich applications that enhance the digital home experience. The cost-effective MPC8313E communications processor family meets the requirements of several small office/home office (SOHO), printing, IP services and industrial control applications. The e300 core complex also includes 16 KB of L1 instruction and data caches and on-chip memory management units (MMUs). None /docs/en/fact-sheet/MPC8313PRPREFS.pdf English 900452 None Fact Sheet 2022-12-07 /docs/en/fact-sheet/MPC8313PRPREFS.pdf MPC8313E PowerQUICC<sup>&#174;</sup> &#8482; II Pro Processor - Fact Sheet /docs/en/fact-sheet/MPC8313PRPREFS.pdf documents 736675474163315314 Fact Sheet N Y en None Y t523 pdf 1 N MPC8313E PowerQUICC<sup>&#174;</sup> &#8482; II Pro Processor - Fact Sheet 900.5 KB MPC8313PRPREFS N 1163535835404734846058 Product Brief 1 /docs/en/product-brief/MPC8313EPB.pdf 2006-12-18 1166473353896717253803 PSP 3 Dec 18, 2006 Product Brief Product Brief This document provides an overview of the MPC8313E PowerQUICC<sup>&#174;</sup> II Pro processor features, including a block diagram showing the major functional components. None /docs/en/product-brief/MPC8313EPB.pdf English 567359 None Product Brief 2022-12-07 /docs/en/product-brief/MPC8313EPB.pdf MPC8313E Product Brief /docs/en/product-brief/MPC8313EPB.pdf documents 899114358132306053 Product Brief N Y en None Y t532 pdf 0 N MPC8313E Product Brief 567.4 KB MPC8313EPB N 1166473353896717253803 Reference Manual 3 /docs/en/reference-manual/e300CORERMAD.pdf 2010-01-20 1264006256879704515314 PSP 5 Jan 20, 2010 Reference Manual This addendum describes corrections to the e300 Power Architecture&#8482; Core Family Reference Manual, Revision 4. None /docs/en/reference-manual/e300CORERMAD.pdf English documents 424614 None 500633505221135046 2022-12-07 /docs/en/reference-manual/e300CORERMAD.pdf Errata to e300 Power Architecture&#8482; Core Family Reference Manual, Rev. 4 /docs/en/reference-manual/e300CORERMAD.pdf documents 500633505221135046 Reference Manual N en None Y pdf 4.1 N Errata to e300 Power Architecture&#8482; Core Family Reference Manual, Rev. 4 424.6 KB E300CORERMAD N 1264006256879704515314 /docs/en/reference-manual/e300coreRM.pdf 2005-04-12 1113346645199746873364 PSP 6 Dec 12, 2007 Reference Manual Supports e300c1, e300c2, e300c3, e300c4. The primary objective of this reference manual is to describe the functionality of the microprocessors in the e300 core family, which are PowerPC &#8482; microprocessors built on Power Architecture &#8482; technology. The e300 designs are based on the MPC603e microprocessor. None /docs/en/reference-manual/e300coreRM.pdf English documents 3862349 None 500633505221135046 2022-12-07 /docs/en/reference-manual/e300coreRM.pdf e300 Power Architecture &#8482; Core Family - Reference Manual /docs/en/reference-manual/e300coreRM.pdf documents 500633505221135046 Reference Manual N en None Y pdf 4 N e300 Power Architecture &#8482; Core Family - Reference Manual 3.9 MB E300CORERM N 1113346645199746873364 /docs/en/reference-manual/MPC8313ERM.pdf 2006-11-14 1163539134457705852596 PSP 2 Aug 4, 2010 Reference Manual Reference Manual This reference manual defines the functionality of the MPC8313E. It is written from the perspective of the MPC8313E, which is the superset device, and unless otherwise noted, the information applies also to the MPC8313. None /docs/en/reference-manual/MPC8313ERM.pdf English 9806645 None Reference Manual 2022-12-07 /docs/en/reference-manual/MPC8313ERM.pdf MPC8313E Reference Manual /docs/en/reference-manual/MPC8313ERM.pdf documents 500633505221135046 Reference Manual N Y en None Y t877 pdf 3 N MPC8313E Reference Manual 9.8 MB MPC8313ERM N 1163539134457705852596 Supporting Information 3 /docs/en/supporting-information/FSLNISTCAVP.pdf 2016-11-09 1368836090577704535160 PSP 32 Oct 28, 2016 Supporting Information FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. None /docs/en/supporting-information/FSLNISTCAVP.pdf English documents 303546 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1.9 N N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 303.5 KB FSLNISTCAVP N 1368836090577704535160 /docs/en/supporting-information/MPC8311_8313PECI.pdf 2010-12-14 1292347737662695465152 PSP 33 Dec 10, 2010 Supporting Information None /docs/en/supporting-information/MPC8311_8313PECI.pdf English documents 12582 None 371282830530968666 2023-06-19 /docs/en/supporting-information/MPC8311_8313PECI.pdf MPC8311_8313 Customer Export Control Info /docs/en/supporting-information/MPC8311_8313PECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 0 N MPC8311_8313 Customer Export Control Info 12.6 KB MPC8311_8313PECI N 1292347737662695465152 /docs/en/supporting-information/MPC8311E_8313EPECI.pdf 2016-10-31 1232680180782714601297 PSP 34 Jan 19, 2009 Supporting Information MPC8313 Customer Export Control Information Document None /docs/en/supporting-information/MPC8311E_8313EPECI.pdf English documents 191492 None 371282830530968666 2023-06-19 N /docs/en/supporting-information/MPC8311E_8313EPECI.pdf MPC8313 Customer Export Control Information /docs/en/supporting-information/MPC8311E_8313EPECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1 N N MPC8313 Customer Export Control Information 191.5 KB MPC8311E_8313EPECI N 1232680180782714601297 White Paper 2 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf 2016-10-31 1227561595497709456436 PSP 35 Aug 15, 2008 White Paper Network security protocols and applications use a variety of cryptographic algorithms to achieve these high-level goals. Because cryptography is computationally intensive, hardware acceleration is highly desirable when cryptographic algorithms are frequent system functions. Registration without Disclaimer /secured/assets/documents/en/white-paper/CRYPTOWP.pdf English documents 580121 None 918633085541740938 2022-12-07 Y /webapp/Download?colCode=CRYPTOWP Understanding Cryptographic Performance /secured/assets/documents/en/white-paper/CRYPTOWP.pdf documents 918633085541740938 White Paper N en Extended Y pdf 3 Y N Understanding Cryptographic Performance 580.1 KB CRYPTOWP N 1227561595497709456436 /docs/en/white-paper/DDRSDRAMWP.pdf 2016-10-31 1208376896761708228520 PSP 36 Apr 16, 2008 White Paper The focus of this white paper is to provide the end user with high level design considerations and/or trade-offs associated with migrating from SDRAM to DDR SDRAM-based designs. None /docs/en/white-paper/DDRSDRAMWP.pdf English documents 735286 None 918633085541740938 2023-06-19 N /docs/en/white-paper/DDRSDRAMWP.pdf Comparison of DDRx and SDRAM /docs/en/white-paper/DDRSDRAMWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N N Comparison of DDRx and SDRAM 735.3 KB DDRSDRAMWP N 1208376896761708228520 true Y Products

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