MCZ33903DD3EK Product Information|NXP

Buy Options

Operating Features

ParameterValue
Device Function
comm transceivers, linear regulators, system basis chip
Data Rate (Max) (Kbps)
1000.0
Supply Voltage [min] (V)
5.5
ParameterValue
Supply Voltage [max] (V)
28
Interface and Input Control
SPI / SPI
Ambient Operating Temperature (Min to Max) (℃)
-40 to 125

Environmental

Part/12NCPbFreeEU RoHSHalogen FreeRHF Indicator2nd Level InterconnectREACH SVHCWeight (mg)
MCZ33903DD3EK(935333163574)
Yes
Yes
Certificate Of Analysis (CoA)
Yes
D
e3
REACH SVHC
472.0
MCZ33903DD3EKR2(935333163518)
Yes
Yes
Certificate Of Analysis (CoA)
Yes
D
e3
REACH SVHC
472.0

Quality

Part/12NCSafe Assure Functional SafetyMoisture Sensitivity Level (MSL)Peak Package Body Temperature (PPT) (C°)Maximum Time at Peak Temperatures (s)
Lead Free SolderingLead Free SolderingLead Free Soldering
MCZ33903DD3EK
(935333163574)
No
3
260
40
MCZ33903DD3EKR2
(935333163518)
No
3
260
40

Shipping

Part/12NCHarmonized Tariff (US)Disclaimer
MCZ33903DD3EK
(935333163574)
854239
MCZ33903DD3EKR2
(935333163518)
854239

Product Change Notice

Part/12NCIssue DateEffective DatePCNTitle
MCZ33903DD3EK
(935333163574)
2025-04-162025-05-26202504007IFreescale Logo to NXP Logo Product Marking Conversion for All Remaining Former Freescale Products
MCZ33903DD3EKR2
(935333163518)
MCZ33903DD3EK
(935333163574)
2020-12-152020-12-16202011011INXP Will Add a Sealed Date to the Product Label
MCZ33903DD3EKR2
(935333163518)
MCZ33903DD3EK
(935333163574)
2017-12-202018-01-03201710023INew PQ Label Input for Non-MPQ Shipments

More about MC33903

The NXP MC33903 is part of a second generation family of system basis chips, combining multiple features and enhanced module design.

  • The MC33903 works as an advanced power management unit for the MCU and additional integrated circuits such as sensors and CAN transceivers
  • Built-in enhanced high-speed CAN interface (ISO11898-2 and -5), with local and bus failure diagnostics, protection and fail-safe operation mode.
  • The SBC may include zero, one or two LIN 2.1 interfaces with LIN output pin switches.