The MPC8306 and MPC8306S are part of the cost-effective MPC830x communications processor family based on the e300 core and built on Power Architecture® technology. The devices integrate QUICC Engine® technology capable of supporting HDLC, TDM and 10/100 R/MII. The MPC8306 also supports IEEE® 1588 v2 time stamping. The MPC8306/S devices provide users with a highly integrated, fully programmable communications processor for use in many networking, industrial control and low-end embedded applications. This helps ensure that a cost-effective system solution can be quickly developed and offers flexibility to accommodate new standards and evolving system requirements.
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Part | Order | CAD Model | Status | Package Type | Package Termination Count | Core Type | Operating Frequency [Max] (MHz) | External Memory Supported | Ambient Operating Temperature (Min to Max) (℃) |
|---|---|---|---|---|---|---|---|---|---|
End of Life | LFBGA369 | 369 | e300 | 133 | — | -40 to 105 | |||
End of Life | LFBGA369 | 369 | e300 | 200 | DDR2 SDRAM, SDRAM | -40 to 105 | |||
End of Life | LFBGA369 | 369 | e300 | 266 | DDR2 SDRAM, SDRAM | -40 to 105 | |||
End of Life | LFBGA369 | 369 | e300 | 333 | DDR2 SDRAM, SDRAM | -40 to 105 | |||
End of Life | LFBGA369 | 369 | e300 | 133 | DDR2 SDRAM, SDRAM | -40 to 105 | |||
End of Life | LFBGA369 | 369 | e300 | 200 | DDR2 SDRAM, SDRAM | -40 to 105 | |||
End of Life | LFBGA369 | 369 | e300 | 266 | DDR2 SDRAM, SDRAM | -40 to 105 | |||
End of Life | LFBGA369 | 369 | e300 | 333 | DDR2 SDRAM, SDRAM | -40 to 105 | |||
End of Life | LFBGA369 | 369 | e300 | 133 | — | 0 to 105 | |||
End of Life | LFBGA369 | 369 | e300 | 200 | — | 0 to 105 |
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