NVT2002TL Product Information|NXP

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NVT2002TLH

Active

12NC: 935291166125

Details

NVT2002TL,118

No Longer Manufactured

12NC: 935291166118

Details

Operating Features

ParameterValue
Signal Application
Open-drain, Push-pull signals
Type VLT
BiDirectional FET
Number of bits
2
VCC(A) (Min - Max)
1 to 3.6
VCC(B) (Min-Max)
1.8 to 5.5
ParameterValue
Bandwidth (Max) (MHz)
33
Input Type (TTL, CMOS, Schmitt Trigger)
CMOS
Output Type (Open Drain, 3-State, Push-Pull, Pass-gate)
3-State, Pass-gate
Ambient Operating Temperature (Min to Max) (℃)
-40 to 105
AEC-Q100 compliant
N

Environmental

Part/12NCPbFreeEU RoHSHalogen FreeRHF IndicatorREACH SVHCWeight (mg)
NVT2002TL,118(935291166118)
No
No
-
REACH SVHC
-
NVT2002TLH(935291166125)
Yes
Yes
Certificate Of Analysis (CoA)
Yes
DREACH SVHC
8.967847999999998

Quality

Part/12NCSafe Assure Functional SafetyMoisture Sensitivity Level (MSL)Peak Package Body Temperature (PPT) (C°)
Lead SolderingLead Free SolderingLead SolderingLead Free Soldering
NVT2002TL,118
(935291166118)
-
-
-
-
-
NVT2002TLH
(935291166125)
No
1
1
240
260

Shipping

Part/12NCHarmonized Tariff (US)Disclaimer
NVT2002TL,118
(935291166118)
854239
NVT2002TLH
(935291166125)
854239

Product Change Notice

Part/12NCIssue DateEffective DatePCNTitle
NVT2002TLH
(935291166125)
2022-12-012022-12-04202210008IData sheet MOQ correction for SOT1052-1 "TL"

More about NVT2001_NVT2002

The NVT2001/02 are bidirectional voltage level translators operational from 1.0 V to 3.6 V (Vref(A)) and 1.8 V to 5.5 V (Vref(B)), which allow bidirectional voltage translations between 1.0 V and 5 V without the need for a direction pin in open-drain or push-pull applications. Bit widths ranging from 1-bit or 2-bit are offered for level translation application with transmission speeds < 33 MHz for an open-drain system with a 50 pF capacitance and a pull-up of 197 Ω.

When the An or Bn port is LOW, the clamp is in the ON-state and a low resistance connection exists between the An and Bn ports. The low ON-state resistance (Ron) of the switch allows connections to be made with minimal propagation delay. Assuming the higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is limited to the voltage set by VREFA. When the An port is HIGH, the Bn port is pulled to the drain pull-up supply voltage (Vpu(D)) by the pull-up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user without the need for directional control.

When EN is HIGH, the translator switch is on, and the An I/O are connected to the Bn I/O, respectively, allowing bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state exists between ports. The EN input circuit is designed to be supplied by Vref(B). To ensure the high-impedance state during power-up or power-down, EN must be LOW.

All channels have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the switch is symmetrical. The translator provides excellent ESD protection to lower voltage devices, and at the same time protects less ESD-resistant devices.