Layerscape® LX2160A, LX2120A, LX2080A Processors | NXP Semiconductors

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Layerscape® LX2160A, LX2120A, LX2080A Processors

LX2160A Active
Arm SystemReady

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The LX2160A multicore processor, the highest-performance member of the Layerscape family, combines FinFET process technology's low power and sixteen Arm® Cortex®-A72 cores with datapath acceleration optimized for L2/3 packet processing, together with security offload, robust traffic management and quality of service.

This advanced sixteen-core 64-bit Arm processor is ideal for applications such as 5G packet processing, network function virtualization (NFV), white-box switching, high-processing industrial computers, machine learning and smart Network Interface Cards. The high level of integration delivers significant performance benefits such as 100 GbE, hardware L2 switching, DPAA2 with 100 Gbps decompression/compression and 50 Gbps SEC and multiple PCIe Gen3.0 and SATA controllers.

For Edge Computing, this processor offers outstanding computing performance with a powerful packet offload and Ethernet controllers. You can have high-end and high-speed communications in one device, with low-speed peripherals such as sensors and the computing power to process and act upon all received information.

Layerscape processors are part of NXP's EdgeVerse™ edge computing platform.

Block Diagram

Layerscape LX2160A Block Diagram

Layerscape LX2160A Block Diagram
Get diagram PDF

Features

  • 16 Cortex-A72 CPU cores, running up to 2.2 GHz
  • 18 MB cache/on-chip memory
  • 24 SerDes lanes, operating up to 25 GHz
  • Up to 16 Ethernet ports
  • Supported Ethernet speeds include 1, 2.5, 10, 25, 40, 50, and 100 gigabits per second
  • 114 Gbps Layer 2 Ethernet switch
  • Up to 24 PCIe Gen3 lanes, supporting ports as wide as x8
  • 50 Gbps security accelerator
  • 100 Gbps data compression/decompression engine
  • Proven certifiable to the Arm SystemReady ES  standard to ensure interoperability with standard operating systems and hypervisors.

Layerscape LX2 Family Comparison Table

LX2160A LX2120A LX2080A
Cores 16 12 8
L2 cache 8MB 6MB 8MB
SerDes 24
PCIe Up to 6x Gen3
DDR 2x DDR4, Up to 3200MT/s, 256GB capacity
Plat cache + PEB 10MB
WRIOP 16 simultaneous MACs; combos of up to 16x 1GE, 10x 1/2.5/10GE, 6x 25GE, or 2x 40/50/100GE; L2 switching up to 114Gbps
SEC Up to 50Gbps
DCE Up to 100Gbps
Package 40 x 40 mm, 1517 pins

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LX2080CA72232B
Data Sheet

Rev 2

LX2160 family

Active

BLBX3-T2

Automotive

10K @ US$297.91

1517

BGA1517

1.0

Arm Cortex-A72

8

2200

—

32, 48

32, 48

8192

256

DDR4 SDRAM

3200

3

2

4

8

2

2

18

100G, 10G, 1G

6

PCIe 3.0

4 x SATA 3.0

N

Y

2

JTAG

-40 to 105

LX2080CC72232B
Data Sheet

Rev 2

LX2160 family

Active

BLBX3-T2

Automotive

10K @ US$312.80

1517

BGA1517

1.0

Arm Cortex-A72

8

2200

—

32, 48

32, 48

8192

256

DDR4 SDRAM

3200

3

2

4

8

2

2

18

100G, 10G, 1G

6

PCIe 3.0

4 x SATA 3.0

Y

Y

2

JTAG

-40 to 105

LX2080SC71826B
Data Sheet

Rev 2

LX2160 family

Active

LX2160A-RDB-B

Industrial

100 @ US$279.82

1517

BGA1517

1.0

Arm Cortex-A72

8

1800

11

32, 48

32, 48

8192

256

DDR4 SDRAM

2600

3

2

4

8

2

2

18

100G, 10G, 1G, 25 Gbit/s

6

PCIe 3.0

4 x SATA 3.0

Y

Y

2

JTAG

0 to 105

LX2080SC72029B
Data Sheet

Rev 2

LX2160 family

Active

LX2160A-RDB-B

Industrial

100 @ US$317.12

1517

BGA1517

1.0

Arm Cortex-A72

8

2000

15.7

32, 48

32, 48

8192

256

DDR4 SDRAM

2900

3

2

4

8

2

2

18

100G, 10G, 1G, 25 Gbit/s

6

PCIe 3.0

4 x SATA 3.0

Y

Y

2

JTAG

0 to 105

LX2080SC72232B
Data Sheet

Rev 2

LX2160 family

Active

LX2160A-RDB-B

Industrial

100 @ US$373.10

1517

BGA1517

1.0

Arm Cortex-A72

8

2200

21.8

32, 48

32, 48

8192

256

DDR4 SDRAM

3200

3

2

4

8

2

2

18

100G, 10G, 1G, 25 Gbit/s

6

PCIe 3.0

4 x SATA 3.0

Y

Y

2

JTAG

0 to 105

LX2080SE71826B
Data Sheet

Rev 2

LX2160 family

Active

LX2160A-RDB-B

Industrial

100 @ US$266.49

1517

BGA1517

1.0

Arm Cortex-A72

8

1800

11

32, 48

32, 48

8192

256

DDR4 SDRAM

2600

3

2

4

8

2

2

18

100G, 10G, 1G, 25 Gbit/s

6

PCIe 3.0

4 x SATA 3.0

Y

Y

2

JTAG

0 to 105

LX2080SE72029B
Data Sheet

Rev 2

LX2160 family

Active

LX2160A-RDB-B

Industrial

100 @ US$302.03

1517

BGA1517

1.0

Arm Cortex-A72

8

2000

15.7

32, 48

32, 48

8192

256

DDR4 SDRAM

2900

3

2

4

8

2

2

18

100G, 10G, 1G, 25 Gbit/s

6

PCIe 3.0

4 x SATA 3.0

Y

Y

2

JTAG

0 to 105

LX2080SE72232B
Data Sheet

Rev 2

LX2160 family

Active

LX2160A-RDB-B

Industrial

100 @ US$355.32

1517

BGA1517

1.0

Arm Cortex-A72

8

2200

21.8

32, 48

32, 48

8192

256

DDR4 SDRAM

3200

3

2

4

8

2

2

18

100G, 10G, 1G, 25 Gbit/s

6

PCIe 3.0

4 x SATA 3.0

Y

Y

2

JTAG

0 to 105

LX2080SN71826B
Data Sheet

Rev 2

LX2160 family

Active

LX2160A-RDB-B

Industrial

100 @ US$253.18

1517

BGA1517

1.0

Arm Cortex-A72

8

1800

11

32, 48

32, 48

8192

256

DDR4 SDRAM

2600

3

2

4

8

2

2

18

100G, 10G, 1G, 25 Gbit/s

6

PCIe 3.0

4 x SATA 3.0

N

Y

2

JTAG

0 to 105

LX2080SN72029B
Data Sheet

Rev 2

LX2160 family

Active

LX2160A-RDB-B

Industrial

100 @ US$286.93

1517

BGA1517

1.0

Arm Cortex-A72

8

2000

15.7

32, 48

32, 48

8192

256

DDR4 SDRAM

2900

3

2

4

8

2

2

18

100G, 10G, 1G, 25 Gbit/s

6

PCIe 3.0

4 x SATA 3.0

N

Y

2

JTAG

0 to 105

N true 0 PSPLX2160Aen 34 Application Note Application Note t789 21 Data Sheet Data Sheet t520 1 Errata Errata t522 1 Fact Sheet Fact Sheet t523 2 Product Brief Product Brief t532 1 Reference Manual Reference Manual t877 3 Supporting Information Supporting Information t531 2 User Manual User Manual t1009 1 White Paper White Paper t530 2 en_US en_US en Data Sheet Data Sheet 1 1 3 English The LX2160A integrated multicore processor combines 16 Arm® Cortex®-A72 processor cores with 24 lanes of the latest 25 GHz SerDes technology. 1595314585613699291945 PSP 1.7 MB Registration without Disclaimer None documents Extended 1595314585613699291945 /secured/assets/documents/en/data-sheet/LX2160A.pdf 1654290 /secured/assets/documents/en/data-sheet/LX2160A.pdf LX2160 documents Y N 2020-07-20 LX2160A, LX2120A, LX2080A Data Sheet /webapp/Download?colCode=LX2160 /secured/assets/documents/en/data-sheet/LX2160A.pdf Data Sheet N 980000996212993340 2023-06-18 pdf Y en Sep 23, 2021 980000996212993340 Data Sheet Y N LX2160A, LX2120A, LX2080A Data Sheet Reference Manual Reference Manual 3 2 1 English The LX2160A processor is built on NXP's software-aware, core-agnostic DPAA2 architecture, which delivers scalable acceleration elements sized for application needs, unprecedented efficiency, and smarter, more capable networks. 1595229391556697418209 PSP 58.0 MB Registration without Disclaimer None documents Extended 1595229391556697418209 /secured/assets/documents/en/reference-manual/LX2160ARM.pdf 57963655 /secured/assets/documents/en/reference-manual/LX2160ARM.pdf LX2160ARM documents Y N 2020-07-20 LX2160A Reference Manual /webapp/Download?colCode=LX2160ARM /secured/assets/documents/en/reference-manual/LX2160ARM.pdf Reference Manual N 500633505221135046 2023-06-18 pdf Y en Oct 6, 2021 500633505221135046 Reference Manual Y N LX2160A Reference Manual 3 0 English SEC is the chip's cryptographic acceleration and offloading hardware and combines cryptographic and other mathematical functions to create a modular and scalable hardware acceleration and assurance engine. 1595230028328718283020 PSP 6.7 MB Registration without Disclaimer None documents Extended 1595230028328718283020 /secured/assets/documents/en/reference-manual/LX2160ASECRM.pdf 6704086 /secured/assets/documents/en/reference-manual/LX2160ASECRM.pdf LX2160ASECRM documents Y N 2020-07-20 LX2160A Security (SEC) Reference Manual /webapp/Download?colCode=LX2160ASECRM /secured/assets/documents/en/reference-manual/LX2160ASECRM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jul 20, 2020 500633505221135046 Reference Manual Y N LX2160A Security (SEC) Reference Manual 4 0 English This document provides information about NXP's second generation Data Path Acceleration Architecture (DPAA2). 1592476874355717141786 PSP 13.9 MB Registration without Disclaimer None documents Extended 1592476874355717141786 /secured/assets/documents/en/reference-manual/LX2160ADPAA2RM.pdf 13931706 /secured/assets/documents/en/reference-manual/LX2160ADPAA2RM.pdf LX2160ADPAA2RM documents Y N 2020-06-18 LX2160A Family Data Path Acceleration Architecture, Second Generation (DPAA2) Low-Level Hardware Reference Manual /webapp/Download?colCode=LX2160ADPAA2RM /secured/assets/documents/en/reference-manual/LX2160ADPAA2RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jun 18, 2020 500633505221135046 Reference Manual Y N LX2160A Family Data Path Acceleration Architecture, Second Generation (DPAA2) Low-Level Hardware Reference Manual Application Note Application Note 21 5 2 English This application note describes the limitations of the Network on Chip application note, AN13749, LX2160A, LS1028A, Performance, NOC, FlexSPI 1668742330675708913956 PSP 121.7 KB Registration without Disclaimer None documents Basic 1668742330675708913956 /secured/assets/documents/en/application-note/AN13749.pdf 121691 /secured/assets/documents/en/application-note/AN13749.pdf AN13749 documents Y N 2022-11-17 Network on Chip (NOC) Performance Caveats /webapp/Download?colCode=AN13749 /secured/assets/documents/en/application-note/AN13749.pdf Application Note N 645036621402383989 2024-03-18 pdf Y en Mar 18, 2024 645036621402383989 Application Note Y N Network on Chip (NOC) Performance Caveats 6 3 English AN5097: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR4 memory subsystem. 1428008859060729157318 PSP 1.1 MB Registration without Disclaimer None documents Extended 1428008859060729157318 /secured/assets/documents/en/application-note/AN5097.pdf 1120906 /secured/assets/documents/en/application-note/AN5097.pdf AN5097 documents Y N 2016-10-31 Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces /webapp/Download?colCode=AN5097 /secured/assets/documents/en/application-note/AN5097.pdf Application Note N 645036621402383989 2024-12-18 pdf Y en Jul 28, 2023 645036621402383989 Application Note Y N Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces 7 1 English AN12750: This application note describes 10GBase-KR link training to get optimal training parameters and the procedure to validate it. 1591185804970704148974 PSP 6.1 MB Registration without Disclaimer None documents Extended 1591185804970704148974 /secured/assets/documents/en/application-note/AN12750.pdf 6058065 /secured/assets/documents/en/application-note/AN12750.pdf AN12750 documents Y N 2020-06-03 Enabling 10GBase-KR on QorIQ Platforms Application Note /webapp/Download?colCode=AN12750 /secured/assets/documents/en/application-note/AN12750.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jul 29, 2022 645036621402383989 Application Note Y N Enabling 10GBase-KR on QorIQ Platforms Application Note 8 0 English appllcation note, AN13684, WRIOP port, WRIOP FIFO depletion, Avoid WRIOP FIFO depletion, 100 Gbps bandwidth configuration, WRIOP 100 Gbps, RECYCLE ports speed change impact, WRIOP FIFO size distribution, WRIOP total FIFO size 1658668288921712850073 PSP 208.4 KB None None documents None 1658668288921712850073 /docs/en/application-note/AN13684.pdf 208437 /docs/en/application-note/AN13684.pdf AN13684 documents N N 2022-07-24 Avoiding WRIOP FIFO Depletion for 100 Gbps Bandwidth Configuration on LX2 Platforms /docs/en/application-note/AN13684.pdf /docs/en/application-note/AN13684.pdf Application Note N 645036621402383989 2024-12-13 pdf N en Jul 5, 2022 645036621402383989 Application Note Y N Avoiding WRIOP FIFO Depletion for 100 Gbps Bandwidth Configuration on LX2 Platforms 9 2 English This document provides recommendations for new designs based on the LX2160A and LX2162A, which are advanced, multicore processors that combine 16 Arm® Cortex®-A72 cores with advanced, high-performance datapath acceleration logic and network and peripheral bus interfaces required for networking, storage, telecom/datacom, wireless infrastructure, and general-purpose embedded applications. 1611135817359728320834 PSP 1.1 MB Registration without Disclaimer None documents Extended 1611135817359728320834 /secured/assets/documents/en/application-note/AN5407.pdf 1078031 /secured/assets/documents/en/application-note/AN5407.pdf AN5407 documents Y N 2021-01-20 AN5407, LX2160A and LX2162A Design Checklist, Application Note /webapp/Download?colCode=AN5407 /secured/assets/documents/en/application-note/AN5407.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Apr 22, 2022 645036621402383989 Application Note Y N AN5407, LX2160A and LX2162A Design Checklist, Application Note 10 0 Chinese 1649067147403724850019zh PSP 155.1 KB None None documents None 1649067147403724850019 /docs/zh/application-note/AN13608.pdf 155124 /docs/zh/application-note/AN13608.pdf AN13608 documents N N 2022-04-04 Chaining FlexTimers on Layerscape Devices /docs/zh/application-note/AN13608.pdf /docs/zh/application-note/AN13608.pdf Application Note N 645036621402383989 2023-09-14 zh Apr 4, 2022 645036621402383989 Application Note Y N 将Layerscape器件上的FlexTimer串接起来 0 English 1649067147403724850019 PSP 155.1 KB None None documents None 1649067147403724850019 /docs/en/application-note/AN13608.pdf 155124 /docs/en/application-note/AN13608.pdf AN13608 documents N N 2022-04-04 Chaining FlexTimers on Layerscape Devices /docs/en/application-note/AN13608.pdf /docs/en/application-note/AN13608.pdf Application Note N 645036621402383989 2023-09-14 pdf N en Apr 4, 2022 645036621402383989 Application Note Y N Chaining FlexTimers on Layerscape Devices 11 4 English AN12572: This document describes how to enable backplane support for Layerscape and QorIQ devices with embedded support for this type of connection. 1567589575242748292636 PSP 194.6 KB None None documents None 1567589575242748292636 /docs/en/application-note/AN12572.pdf 194553 /docs/en/application-note/AN12572.pdf AN12572 documents N N 2019-09-04 Ethernet Backplane Driver Support Application Note /docs/en/application-note/AN12572.pdf /docs/en/application-note/AN12572.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 26, 2021 645036621402383989 Application Note Y N Ethernet Backplane Driver Support Application Note 12 0 English 1631544294418735262217 PSP 960.7 KB None None documents None 1631544294418735262217 /docs/en/application-note/AN13329.pdf 960672 /docs/en/application-note/AN13329.pdf AN13329 documents N N 2021-09-13 Network subsystem troubleshooting on DPAA2 devices (illustrated with LX2160) /docs/en/application-note/AN13329.pdf /docs/en/application-note/AN13329.pdf Application Note N 645036621402383989 2024-12-13 pdf N en Sep 13, 2021 645036621402383989 Application Note Y N Network subsystem troubleshooting on DPAA2 devices (illustrated with LX2160) 13 0 Chinese The intent of this document is to provide the necessary information to hardware, software, and system engineers to run the Xen hypervisor on NXP Layerscape platforms. In this action, we consider basic scenarios, such as basic domain management, dom0less, and device passthrough. 1615209347110741342432zh PSP 194.9 KB None None documents None 1615209347110741342432 /docs/zh/application-note/AN13138.pdf 194894 /docs/zh/application-note/AN13138.pdf AN13138 documents N N 2021-03-08 Xen Deployment on Layerscape Platforms /docs/zh/application-note/AN13138.pdf /docs/zh/application-note/AN13138.pdf Application Note N 645036621402383989 2024-12-13 zh Mar 8, 2021 645036621402383989 Application Note Y N 在Layerscape平台上部署Xen 0 English The intent of this document is to provide the necessary information to hardware, software, and system engineers to run the Xen hypervisor on NXP Layerscape platforms. In this action, we consider basic scenarios, such as basic domain management, dom0less, and device passthrough. 1615209347110741342432 PSP 194.9 KB None None documents None 1615209347110741342432 /docs/en/application-note/AN13138.pdf 194894 /docs/en/application-note/AN13138.pdf AN13138 documents N N 2021-03-08 Xen Deployment on Layerscape Platforms /docs/en/application-note/AN13138.pdf /docs/en/application-note/AN13138.pdf Application Note N 645036621402383989 2024-12-13 pdf N en Mar 8, 2021 645036621402383989 Application Note Y N Xen Deployment on Layerscape Platforms 14 0 English application note, AN13031, SDHC, SD card, AC timing with a voltage translator 1612844458694739251362 PSP 230.3 KB None None documents None 1612844458694739251362 /docs/en/application-note/AN13031.pdf 230317 /docs/en/application-note/AN13031.pdf AN13031 documents N N 2021-02-08 Recommendations for SD Connections to 1.8 V SDHC Interfaces Data Sheet /docs/en/application-note/AN13031.pdf /docs/en/application-note/AN13031.pdf Application Note N 645036621402383989 2024-12-13 pdf N en Feb 5, 2021 645036621402383989 Application Note Y N Recommendations for SD Connections to 1.8 V SDHC Interfaces Data Sheet 15 1 English AN12950: This document is intended to serve as a guide to help users configure SerDes equalization settings that are optimal for 25 GbE, 50 GbE, and 100 GbE protocols with an emphasis on tuning transmit equalization parameters. 1600358724323722927383 PSP 848.4 KB None None documents None 1600358724323722927383 /docs/en/application-note/AN12950.pdf 848430 /docs/en/application-note/AN12950.pdf AN12950 documents N N 2020-09-17 Optimizing Serial Interface Equalization Settings for 25 GbE on LX216xA Processor Application Note /docs/en/application-note/AN12950.pdf /docs/en/application-note/AN12950.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Dec 2, 2020 645036621402383989 Application Note Y N Optimizing Serial Interface Equalization Settings for 25 GbE on LX216xA Processor Application Note 16 0 Chinese AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ<sup>&#174;</sup> platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105zh PSP 1.0 MB None None documents None 1456317293250700197105 /docs/zh/application-note/AN5260.pdf 1027928 /docs/zh/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/zh/application-note/AN5260.pdf /docs/zh/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 zh Feb 24, 2016 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 1 English AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105 PSP 1.0 MB None None documents None 1456317293250700197105 /docs/en/application-note/AN5260.pdf 1027928 /docs/en/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf /docs/en/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 30, 2020 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 17 0 English AN13022: This document describes the sequence to reconfigure SerDes lanes from SGMII to USXGMII/XFI and two PCIe x2 lanes at Gen 1 or Gen 2 speeds for the LX2160A device. 1603264143926739033731 PSP 142.1 KB None None documents None 1603264143926739033731 /docs/en/application-note/AN13022.pdf 142065 /docs/en/application-note/AN13022.pdf AN13022 documents N N 2020-10-21 LX2160A SerDes 1 Lane Reconfiguration from 11 to 31 Application Note /docs/en/application-note/AN13022.pdf /docs/en/application-note/AN13022.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Oct 20, 2020 645036621402383989 Application Note Y N LX2160A SerDes 1 Lane Reconfiguration from 11 to 31 Application Note 18 0 English AN12628: This application note explains how to optimize memory copy routines. 1573117464705697840062 PSP 485.1 KB None None documents None 1573117464705697840062 /docs/en/application-note/AN12628.pdf 485139 /docs/en/application-note/AN12628.pdf AN12628 documents N N 2019-11-07 Optimizing Memory Copy Routines Application Note /docs/en/application-note/AN12628.pdf /docs/en/application-note/AN12628.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 6, 2019 645036621402383989 Application Note Y N Optimizing Memory Copy Routines Application Note 19 1 English Solder joint and package temperature for Pb-free BGA in SnPB and Pb-free solders in IR or convection reflow ovens are discussed in this document. 1154542630989715908212 PSP 281.6 KB None None documents None 1154542630989715908212 /docs/en/application-note/AN3300.pdf 281637 /docs/en/application-note/AN3300.pdf AN3300 documents N N 2017-08-17 General soldering Temperature Process Guidelines /docs/en/application-note/AN3300.pdf /docs/en/application-note/AN3300.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Aug 16, 2017 645036621402383989 Application Note Y N General soldering Temperature Process Guidelines 20 0 English This application note presents configuration and example use cases of L2 switch (DPSW) and Edge Virtual Bridge (DPDMUX). 1500359342664720853564 PSP 650.1 KB Registration without Disclaimer None documents Extended 1500359342664720853564 /secured/assets/documents/en/application-note/AN11979.pdf 650083 /secured/assets/documents/en/application-note/AN11979.pdf AN11979 documents Y N 2017-07-17 AN11979, DPAA2 Ethernet Switch and Edge Virtual Bridge - Application Note /webapp/Download?colCode=AN11979 /secured/assets/documents/en/application-note/AN11979.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jul 18, 2017 645036621402383989 Application Note Y N AN11979, DPAA2 Ethernet Switch and Edge Virtual Bridge - Application Note 21 0 English AN5199: This document targets customers familiar with DPAA1 who would like to know more about DPAA2 before migrating to DPAA2 enabled devices. 1450813697769731607959 PSP 922.3 KB Registration without Disclaimer None documents Extended 1450813697769731607959 /secured/assets/documents/en/application-note/AN5199.pdf 922254 /secured/assets/documents/en/application-note/AN5199.pdf AN5199 documents Y N 2016-10-31 AN5199, Key Concepts for the Transition from DPAA1 to DPAA2 - Application Note /webapp/Download?colCode=AN5199 /secured/assets/documents/en/application-note/AN5199.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Dec 22, 2015 645036621402383989 Application Note Y N AN5199, Key Concepts for the Transition from DPAA1 to DPAA2 - Application Note 22 0 English AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. 1441302193437732651194 PSP 566.4 KB None None documents None 1441302193437732651194 /docs/en/application-note/AN5125.pdf 566365 /docs/en/application-note/AN5125.pdf AN5125 documents N N 2016-10-31 AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf /docs/en/application-note/AN5125.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Sep 3, 2015 645036621402383989 Application Note Y N AN5125, Introduction to Device Trees - Application Note 23 Rev. 0 English This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. 1305312143395731535528 PSP 577.2 KB Registration without Disclaimer None documents Extended 1305312143395731535528 /secured/assets/documents/en/application-note/AN4311.pdf 577164 /secured/assets/documents/en/application-note/AN4311.pdf AN4311 documents Y N 2016-10-31 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /webapp/Download?colCode=AN4311 /secured/assets/documents/en/application-note/AN4311.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 13, 2011 645036621402383989 Application Note Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 24 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939 /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors 25 0 English This document demonstrates how to determine the package temperature and thermal mass dependent moisture sensitivity level (MSL) of products to ensure reliable processing of moisture sensitive surface mount components. Comply with these recommendations to maintain package integrity of components during any heat exposure of board soldering and de-soldering. 1154542628855726115465 PSP 151.6 KB None None documents None 1154542628855726115465 /docs/en/application-note/AN3298.pdf 151612 /docs/en/application-note/AN3298.pdf AN3298 documents N N 2016-10-31 Solder Joint Temperature and Package Peak Temperature /docs/en/application-note/AN3298.pdf /docs/en/application-note/AN3298.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Aug 2, 2006 645036621402383989 Application Note Y N Solder Joint Temperature and Package Peak Temperature User Manual User Manual 1 26 53 English DPAA2 is a hardware-level networking architecture found on some NXP SoCs. This document provides technical information on this architecture mainly for software developers. 1582785451078700466276 PSP 6.0 MB Registration without Disclaimer None documents Extended 1582785451078700466276 /secured/assets/documents/en/user-guide/DPAA2UM.pdf 5987656 /secured/assets/documents/en/user-guide/DPAA2UM.pdf DPAA2UM documents Y N 2020-02-26 DPAA2 User Manual /webapp/Download?colCode=DPAA2UM /secured/assets/documents/en/user-guide/DPAA2UM.pdf User Manual N 309919593431037931 2023-09-21 pdf Y en Sep 19, 2023 309919593431037931 User Manual Y N DPAA2 User Manual Errata Errata 1 27 kb 3 English The current errata for LX2160A, released Feb 2023, Rev 3 It is an NDA document. Please see the Sharepoint site https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx (NDA and NXP-issued invite required), or contact your NXP representative. 1645462883761725451760 PSP None None documents None 1645462883761725451760 https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx LX2160A-ERRATA-LINK documents N N N 2022-02-21 LX2160A Errata https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx Y Errata N 155452329886410597 Y 2023-05-23 URL en May 22, 2023 155452329886410597 Errata Y N https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx LX2160A Errata URL Fact Sheet Fact Sheet 2 28 0 English Non Terrestrial Network (NTN) is a market where NXP products are well-positioned, with continued focus on power efficiency and reliable compute. 1723230543628708110179 PSP 279.3 KB None None documents Override 1723230543628708110179 /docs/en/fact-sheet/1799386-CS_Non terrestrial networks NTN Fact Sheet-LR.pdf 279270 /docs/en/fact-sheet/1799386-CS_Non terrestrial networks NTN Fact Sheet-LR.pdf NTN-FS documents N 2024-08-09 Non-Terrestrial Networking: Extending the Internet to Space /docs/en/fact-sheet/1799386-CS_Non terrestrial networks NTN Fact Sheet-LR.pdf /docs/en/fact-sheet/1799386-CS_Non terrestrial networks NTN Fact Sheet-LR.pdf Fact Sheet N 736675474163315314 2024-08-09 pdf en Aug 5, 2024 736675474163315314 Fact Sheet Y N Non-Terrestrial Networking: Extending the Internet to Space 29 0 Chinese The Layerscape LX2160A SoC delivers the high-performance needed for computeintensive networking applications. Equipped with sixteen Armv8 Cortex-A72 CPU cores, 28 GHz SerDes technology and low FinFET power, this processor supports up to 100 Gbit/s Ethernet and the latest PCIe Gen4 technology. 1507217881724718214358zh PSP 4.9 MB None None documents None 1507217881724718214358 /docs/zh/fact-sheet/LX2160AFS.pdf 4948764 /docs/zh/fact-sheet/LX2160AFS.pdf LX2160AFS documents N N 2017-10-05 Layerscape LX2160A Processor Fact Sheet /docs/zh/fact-sheet/LX2160AFS.pdf /docs/zh/fact-sheet/LX2160AFS.pdf Fact Sheet N 736675474163315314 2022-12-07 zh Oct 5, 2017 736675474163315314 Fact Sheet N QorIQ Layerscape LX2160A Processor Fact Sheet 2 English The Layerscape LX2160A SoC delivers the high-performance needed for computeintensive networking applications. Equipped with sixteen Armv8 Cortex-A72 CPU cores, 28 GHz SerDes technology and low FinFET power, this processor supports up to 100 Gbit/s Ethernet and the latest PCIe Gen4 technology. 1507217881724718214358 PSP 4.9 MB None None documents None 1507217881724718214358 /docs/en/fact-sheet/LX2160AFS.pdf 4948764 /docs/en/fact-sheet/LX2160AFS.pdf LX2160AFS documents N N 2017-10-05 Layerscape LX2160A Processor Fact Sheet /docs/en/fact-sheet/LX2160AFS.pdf /docs/en/fact-sheet/LX2160AFS.pdf Fact Sheet N 736675474163315314 2022-12-07 pdf N en Dec 22, 2021 736675474163315314 Fact Sheet Y N Layerscape LX2160A Processor Fact Sheet Product Brief Product Brief 1 30 0 English This document describes ASF IPsec acceleration implementation on LX2160 processor. It also lists the use cases, performance setup, and performance values obtained for this processor. 1675990574992703992043 PSP 594.6 KB Registration without Disclaimer None documents Extended 1675990574992703992043 /secured/assets/documents/en/product-brief/LX2160ASFSIBPB_Rev0.pdf 594554 /secured/assets/documents/en/product-brief/LX2160ASFSIBPB_Rev0.pdf LX2160ASFSIBPB documents Y N 2023-02-09 LX2160-based Application Specific Fastpath for Small Cell IPsec Backhaul Product Brief /webapp/Download?colCode=LX2160ASFSIBPB /secured/assets/documents/en/product-brief/LX2160ASFSIBPB_Rev0.pdf Product Brief N 899114358132306053 2023-07-24 pdf Y en Feb 3, 2023 899114358132306053 Product Brief Y N LX2160-based Application Specific Fastpath for Small Cell IPsec Backhaul Product Brief Supporting Information Supporting Information 2 31 1 English LX2160A, 2120A, 2080A Family Export Control Information 1534961268333709344687 PSP 90.1 KB None None documents None 1534961268333709344687 /docs/en/supporting-information/LX2160A_2120A_2080A-PECI.pdf 90111 /docs/en/supporting-information/LX2160A_2120A_2080A-PECI.pdf LX2160A_2120A_2080A-PECI documents N N 2018-08-22 LX2160A, 2120A, 2080A Family Export Control Information /docs/en/supporting-information/LX2160A_2120A_2080A-PECI.pdf /docs/en/supporting-information/LX2160A_2120A_2080A-PECI.pdf Supporting Information N 371282830530968666 2023-06-19 pdf N en Aug 22, 2018 371282830530968666 Supporting Information Y N LX2160A, 2120A, 2080A Family Export Control Information 32 1.9 English FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. 1368836090577704535160 PSP 303.5 KB None None documents None 1368836090577704535160 /docs/en/supporting-information/FSLNISTCAVP.pdf 303546 /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP documents N N 2016-11-09 FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf /docs/en/supporting-information/FSLNISTCAVP.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 28, 2016 371282830530968666 Supporting Information Y N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper White Paper White Paper 2 33 1.0 English HOW TO SCULPT A 16-CORE 2 GHZ PROCESSOR 1530198601380706887406 PSP 607.1 KB None None documents None 1530198601380706887406 /docs/en/product-brief/EDN-SCULPT-16CORE-PROCESSOR.pdf 607144 /docs/en/product-brief/EDN-SCULPT-16CORE-PROCESSOR.pdf EDN-SCULPT-16CORE-PROCESSOR documents N N 2018-06-28 HOW TO SCULPT A 16-CORE 2 GHZ PROCESSOR /docs/en/product-brief/EDN-SCULPT-16CORE-PROCESSOR.pdf /docs/en/product-brief/EDN-SCULPT-16CORE-PROCESSOR.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Jun 28, 2018 918633085541740938 White Paper Y N HOW TO SCULPT A 16-CORE 2 GHZ PROCESSOR 34 1 English NXP is chasing high-end networking with its newest QorIQ processor, the LX2160A. Sporting 16 Arm<sup>®</sup> Cortex<sup>®</sup>-A72 cores, 100 Gigabit Ethernet, a 16-port Layer 2 switch, and faster acceleration for cryptography and data compres-sion, it will be the company’s largest and fastest multicore embedded processor when it begins production—in mid-2019, by our estimate. 1510277371621724576420 PSP 604.6 KB None None documents None 1510277371621724576420 /docs/en/supporting-information/LX2160A-NXP-Biggest-Multicore.pdf 604575 /docs/en/supporting-information/LX2160A-NXP-Biggest-Multicore.pdf LX2160A-NXP-BM documents N N 2017-11-09 LX2160A NXP's Biggest Multicore /docs/en/supporting-information/LX2160A-NXP-Biggest-Multicore.pdf /docs/en/supporting-information/LX2160A-NXP-Biggest-Multicore.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Nov 9, 2017 918633085541740938 White Paper Y N LX2160A NXP's Biggest Multicore false 0 LX2160A downloads en true 1 Y PSP Y Application Note 21 /secured/assets/documents/en/application-note/AN13749.pdf 2022-11-17 1668742330675708913956 PSP 5 Mar 18, 2024 Application Note This application note describes the limitations of the Network on Chip application note, AN13749, LX2160A, LS1028A, Performance, NOC, FlexSPI Registration without Disclaimer /secured/assets/documents/en/application-note/AN13749.pdf English documents 121691 None 645036621402383989 2024-03-18 Y /webapp/Download?colCode=AN13749 Network on Chip (NOC) Performance Caveats /secured/assets/documents/en/application-note/AN13749.pdf documents 645036621402383989 Application Note N en Basic Y pdf 2 Y N Network on Chip (NOC) Performance Caveats 121.7 KB AN13749 N 1668742330675708913956 /secured/assets/documents/en/application-note/AN5097.pdf 2016-10-31 1428008859060729157318 PSP 6 Jul 28, 2023 Application Note AN5097: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR4 memory subsystem. Registration without Disclaimer /secured/assets/documents/en/application-note/AN5097.pdf English documents 1120906 None 645036621402383989 2024-12-18 Y /webapp/Download?colCode=AN5097 Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces /secured/assets/documents/en/application-note/AN5097.pdf documents 645036621402383989 Application Note N en Extended Y pdf 3 Y N Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces 1.1 MB AN5097 N 1428008859060729157318 /secured/assets/documents/en/application-note/AN12750.pdf 2020-06-03 1591185804970704148974 PSP 7 Jul 29, 2022 Application Note AN12750: This application note describes 10GBase-KR link training to get optimal training parameters and the procedure to validate it. Registration without Disclaimer /secured/assets/documents/en/application-note/AN12750.pdf English documents 6058065 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN12750 Enabling 10GBase-KR on QorIQ Platforms Application Note /secured/assets/documents/en/application-note/AN12750.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N Enabling 10GBase-KR on QorIQ Platforms Application Note 6.1 MB AN12750 N 1591185804970704148974 /docs/en/application-note/AN13684.pdf 2022-07-24 1658668288921712850073 PSP 8 Jul 5, 2022 Application Note appllcation note, AN13684, WRIOP port, WRIOP FIFO depletion, Avoid WRIOP FIFO depletion, 100 Gbps bandwidth configuration, WRIOP 100 Gbps, RECYCLE ports speed change impact, WRIOP FIFO size distribution, WRIOP total FIFO size None /docs/en/application-note/AN13684.pdf English documents 208437 None 645036621402383989 2024-12-13 N /docs/en/application-note/AN13684.pdf Avoiding WRIOP FIFO Depletion for 100 Gbps Bandwidth Configuration on LX2 Platforms /docs/en/application-note/AN13684.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Avoiding WRIOP FIFO Depletion for 100 Gbps Bandwidth Configuration on LX2 Platforms 208.4 KB AN13684 N 1658668288921712850073 /secured/assets/documents/en/application-note/AN5407.pdf 2021-01-20 1611135817359728320834 PSP 9 Apr 22, 2022 Application Note This document provides recommendations for new designs based on the LX2160A and LX2162A, which are advanced, multicore processors that combine 16 Arm® Cortex®-A72 cores with advanced, high-performance datapath acceleration logic and network and peripheral bus interfaces required for networking, storage, telecom/datacom, wireless infrastructure, and general-purpose embedded applications. Registration without Disclaimer /secured/assets/documents/en/application-note/AN5407.pdf English documents 1078031 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN5407 AN5407, LX2160A and LX2162A Design Checklist, Application Note /secured/assets/documents/en/application-note/AN5407.pdf documents 645036621402383989 Application Note N en Extended Y pdf 2 Y N AN5407, LX2160A and LX2162A Design Checklist, Application Note 1.1 MB AN5407 N 1611135817359728320834 /docs/en/application-note/AN13608.pdf 2022-04-04 1649067147403724850019 PSP 10 Apr 4, 2022 Application Note None /docs/en/application-note/AN13608.pdf English documents 155124 None 645036621402383989 2023-09-14 N /docs/en/application-note/AN13608.pdf Chaining FlexTimers on Layerscape Devices /docs/en/application-note/AN13608.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Chaining FlexTimers on Layerscape Devices 155.1 KB AN13608 N 1649067147403724850019 /docs/en/application-note/AN12572.pdf 2019-09-04 1567589575242748292636 PSP 11 Nov 26, 2021 Application Note AN12572: This document describes how to enable backplane support for Layerscape and QorIQ devices with embedded support for this type of connection. None /docs/en/application-note/AN12572.pdf English documents 194553 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN12572.pdf Ethernet Backplane Driver Support Application Note /docs/en/application-note/AN12572.pdf documents 645036621402383989 Application Note N en None Y pdf 4 N N Ethernet Backplane Driver Support Application Note 194.6 KB AN12572 N 1567589575242748292636 /docs/en/application-note/AN13329.pdf 2021-09-13 1631544294418735262217 PSP 12 Sep 13, 2021 Application Note None /docs/en/application-note/AN13329.pdf English documents 960672 None 645036621402383989 2024-12-13 N /docs/en/application-note/AN13329.pdf Network subsystem troubleshooting on DPAA2 devices (illustrated with LX2160) /docs/en/application-note/AN13329.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Network subsystem troubleshooting on DPAA2 devices (illustrated with LX2160) 960.7 KB AN13329 N 1631544294418735262217 /docs/en/application-note/AN13138.pdf 2021-03-08 1615209347110741342432 PSP 13 Mar 8, 2021 Application Note The intent of this document is to provide the necessary information to hardware, software, and system engineers to run the Xen hypervisor on NXP Layerscape platforms. In this action, we consider basic scenarios, such as basic domain management, dom0less, and device passthrough. None /docs/en/application-note/AN13138.pdf English documents 194894 None 645036621402383989 2024-12-13 N /docs/en/application-note/AN13138.pdf Xen Deployment on Layerscape Platforms /docs/en/application-note/AN13138.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Xen Deployment on Layerscape Platforms 194.9 KB AN13138 N 1615209347110741342432 /docs/en/application-note/AN13031.pdf 2021-02-08 1612844458694739251362 PSP 14 Feb 5, 2021 Application Note application note, AN13031, SDHC, SD card, AC timing with a voltage translator None /docs/en/application-note/AN13031.pdf English documents 230317 None 645036621402383989 2024-12-13 N /docs/en/application-note/AN13031.pdf Recommendations for SD Connections to 1.8 V SDHC Interfaces Data Sheet /docs/en/application-note/AN13031.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Recommendations for SD Connections to 1.8 V SDHC Interfaces Data Sheet 230.3 KB AN13031 N 1612844458694739251362 /docs/en/application-note/AN12950.pdf 2020-09-17 1600358724323722927383 PSP 15 Dec 2, 2020 Application Note AN12950: This document is intended to serve as a guide to help users configure SerDes equalization settings that are optimal for 25 GbE, 50 GbE, and 100 GbE protocols with an emphasis on tuning transmit equalization parameters. None /docs/en/application-note/AN12950.pdf English documents 848430 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN12950.pdf Optimizing Serial Interface Equalization Settings for 25 GbE on LX216xA Processor Application Note /docs/en/application-note/AN12950.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N Optimizing Serial Interface Equalization Settings for 25 GbE on LX216xA Processor Application Note 848.4 KB AN12950 N 1600358724323722927383 /docs/en/application-note/AN5260.pdf 2016-10-31 1456317293250700197105 PSP 16 Nov 30, 2020 Application Note AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). None /docs/en/application-note/AN5260.pdf English documents 1027928 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5260.pdf PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N PBL Configuration using QCVS Application Note 1.0 MB AN5260 N 1456317293250700197105 /docs/en/application-note/AN13022.pdf 2020-10-21 1603264143926739033731 PSP 17 Oct 20, 2020 Application Note AN13022: This document describes the sequence to reconfigure SerDes lanes from SGMII to USXGMII/XFI and two PCIe x2 lanes at Gen 1 or Gen 2 speeds for the LX2160A device. None /docs/en/application-note/AN13022.pdf English documents 142065 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN13022.pdf LX2160A SerDes 1 Lane Reconfiguration from 11 to 31 Application Note /docs/en/application-note/AN13022.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N LX2160A SerDes 1 Lane Reconfiguration from 11 to 31 Application Note 142.1 KB AN13022 N 1603264143926739033731 /docs/en/application-note/AN12628.pdf 2019-11-07 1573117464705697840062 PSP 18 Nov 6, 2019 Application Note AN12628: This application note explains how to optimize memory copy routines. None /docs/en/application-note/AN12628.pdf English documents 485139 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN12628.pdf Optimizing Memory Copy Routines Application Note /docs/en/application-note/AN12628.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Optimizing Memory Copy Routines Application Note 485.1 KB AN12628 N 1573117464705697840062 /docs/en/application-note/AN3300.pdf 2017-08-17 1154542630989715908212 PSP 19 Aug 16, 2017 Application Note Solder joint and package temperature for Pb-free BGA in SnPB and Pb-free solders in IR or convection reflow ovens are discussed in this document. None /docs/en/application-note/AN3300.pdf English documents 281637 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3300.pdf General soldering Temperature Process Guidelines /docs/en/application-note/AN3300.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N General soldering Temperature Process Guidelines 281.6 KB AN3300 N 1154542630989715908212 /secured/assets/documents/en/application-note/AN11979.pdf 2017-07-17 1500359342664720853564 PSP 20 Jul 18, 2017 Application Note This application note presents configuration and example use cases of L2 switch (DPSW) and Edge Virtual Bridge (DPDMUX). Registration without Disclaimer /secured/assets/documents/en/application-note/AN11979.pdf English documents 650083 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN11979 AN11979, DPAA2 Ethernet Switch and Edge Virtual Bridge - Application Note /secured/assets/documents/en/application-note/AN11979.pdf documents 645036621402383989 Application Note N en Extended Y pdf 0 Y N AN11979, DPAA2 Ethernet Switch and Edge Virtual Bridge - Application Note 650.1 KB AN11979 N 1500359342664720853564 /secured/assets/documents/en/application-note/AN5199.pdf 2016-10-31 1450813697769731607959 PSP 21 Dec 22, 2015 Application Note AN5199: This document targets customers familiar with DPAA1 who would like to know more about DPAA2 before migrating to DPAA2 enabled devices. Registration without Disclaimer /secured/assets/documents/en/application-note/AN5199.pdf English documents 922254 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN5199 AN5199, Key Concepts for the Transition from DPAA1 to DPAA2 - Application Note /secured/assets/documents/en/application-note/AN5199.pdf documents 645036621402383989 Application Note N en Extended Y pdf 0 Y N AN5199, Key Concepts for the Transition from DPAA1 to DPAA2 - Application Note 922.3 KB AN5199 N 1450813697769731607959 /docs/en/application-note/AN5125.pdf 2016-10-31 1441302193437732651194 PSP 22 Sep 3, 2015 Application Note AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. None /docs/en/application-note/AN5125.pdf English documents 566365 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5125.pdf AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N AN5125, Introduction to Device Trees - Application Note 566.4 KB AN5125 N 1441302193437732651194 /secured/assets/documents/en/application-note/AN4311.pdf 2016-10-31 1305312143395731535528 PSP 23 May 13, 2011 Application Note This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4311.pdf English documents 577164 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4311 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /secured/assets/documents/en/application-note/AN4311.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev. 0 Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 577.2 KB AN4311 N 1305312143395731535528 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 24 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939 DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 /docs/en/application-note/AN3298.pdf 2016-10-31 1154542628855726115465 PSP 25 Aug 2, 2006 Application Note This document demonstrates how to determine the package temperature and thermal mass dependent moisture sensitivity level (MSL) of products to ensure reliable processing of moisture sensitive surface mount components. Comply with these recommendations to maintain package integrity of components during any heat exposure of board soldering and de-soldering. None /docs/en/application-note/AN3298.pdf English documents 151612 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3298.pdf Solder Joint Temperature and Package Peak Temperature /docs/en/application-note/AN3298.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Solder Joint Temperature and Package Peak Temperature 151.6 KB AN3298 N 1154542628855726115465 Data Sheet 1 /secured/assets/documents/en/data-sheet/LX2160A.pdf 2020-07-20 1595314585613699291945 PSP 1 Sep 23, 2021 Data Sheet The LX2160A integrated multicore processor combines 16 Arm® Cortex®-A72 processor cores with 24 lanes of the latest 25 GHz SerDes technology. Registration without Disclaimer /secured/assets/documents/en/data-sheet/LX2160A.pdf English documents 1654290 None 980000996212993340 2023-06-18 Y /webapp/Download?colCode=LX2160 LX2160A, LX2120A, LX2080A Data Sheet /secured/assets/documents/en/data-sheet/LX2160A.pdf documents 980000996212993340 Data Sheet N en Extended Y pdf 3 Y N LX2160A, LX2120A, LX2080A Data Sheet 1.7 MB LX2160 N 1595314585613699291945 Errata 1 https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx 2022-02-21 1645462883761725451760 PSP 27 May 22, 2023 Errata The current errata for LX2160A, released Feb 2023, Rev 3 It is an NDA document. Please see the Sharepoint site https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx (NDA and NXP-issued invite required), or contact your NXP representative. URL None https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx English documents kb None 155452329886410597 2023-05-23 N https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx LX2160A Errata https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx documents 155452329886410597 Errata N en None Y Y N URL 3 N LX2160A Errata Y LX2160A-ERRATA-LINK N https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx 1645462883761725451760 Fact Sheet 2 /docs/en/fact-sheet/1799386-CS_Non terrestrial networks NTN Fact Sheet-LR.pdf 2024-08-09 1723230543628708110179 PSP 28 Aug 5, 2024 Fact Sheet Non Terrestrial Network (NTN) is a market where NXP products are well-positioned, with continued focus on power efficiency and reliable compute. None /docs/en/fact-sheet/1799386-CS_Non terrestrial networks NTN Fact Sheet-LR.pdf English documents 279270 None 736675474163315314 2024-08-09 /docs/en/fact-sheet/1799386-CS_Non terrestrial networks NTN Fact Sheet-LR.pdf Non-Terrestrial Networking: Extending the Internet to Space /docs/en/fact-sheet/1799386-CS_Non terrestrial networks NTN Fact Sheet-LR.pdf documents 736675474163315314 Fact Sheet N en Override Y pdf 0 N Non-Terrestrial Networking: Extending the Internet to Space 279.3 KB NTN-FS N 1723230543628708110179 /docs/en/fact-sheet/LX2160AFS.pdf 2017-10-05 1507217881724718214358 PSP 29 Dec 22, 2021 Fact Sheet The Layerscape LX2160A SoC delivers the high-performance needed for computeintensive networking applications. Equipped with sixteen Armv8 Cortex-A72 CPU cores, 28 GHz SerDes technology and low FinFET power, this processor supports up to 100 Gbit/s Ethernet and the latest PCIe Gen4 technology. None /docs/en/fact-sheet/LX2160AFS.pdf English documents 4948764 None 736675474163315314 2022-12-07 N /docs/en/fact-sheet/LX2160AFS.pdf Layerscape LX2160A Processor Fact Sheet /docs/en/fact-sheet/LX2160AFS.pdf documents 736675474163315314 Fact Sheet N en None Y pdf 2 N N Layerscape LX2160A Processor Fact Sheet 4.9 MB LX2160AFS N 1507217881724718214358 Product Brief 1 /secured/assets/documents/en/product-brief/LX2160ASFSIBPB_Rev0.pdf 2023-02-09 1675990574992703992043 PSP 30 Feb 3, 2023 Product Brief This document describes ASF IPsec acceleration implementation on LX2160 processor. It also lists the use cases, performance setup, and performance values obtained for this processor. Registration without Disclaimer /secured/assets/documents/en/product-brief/LX2160ASFSIBPB_Rev0.pdf English documents 594554 None 899114358132306053 2023-07-24 Y /webapp/Download?colCode=LX2160ASFSIBPB LX2160-based Application Specific Fastpath for Small Cell IPsec Backhaul Product Brief /secured/assets/documents/en/product-brief/LX2160ASFSIBPB_Rev0.pdf documents 899114358132306053 Product Brief N en Extended Y pdf 0 Y N LX2160-based Application Specific Fastpath for Small Cell IPsec Backhaul Product Brief 594.6 KB LX2160ASFSIBPB N 1675990574992703992043 Reference Manual 3 /secured/assets/documents/en/reference-manual/LX2160ARM.pdf 2020-07-20 1595229391556697418209 PSP 2 Oct 6, 2021 Reference Manual The LX2160A processor is built on NXP's software-aware, core-agnostic DPAA2 architecture, which delivers scalable acceleration elements sized for application needs, unprecedented efficiency, and smarter, more capable networks. Registration without Disclaimer /secured/assets/documents/en/reference-manual/LX2160ARM.pdf English documents 57963655 None 500633505221135046 2023-06-18 Y /webapp/Download?colCode=LX2160ARM LX2160A Reference Manual /secured/assets/documents/en/reference-manual/LX2160ARM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 1 Y N LX2160A Reference Manual 58.0 MB LX2160ARM N 1595229391556697418209 /secured/assets/documents/en/reference-manual/LX2160ASECRM.pdf 2020-07-20 1595230028328718283020 PSP 3 Jul 20, 2020 Reference Manual SEC is the chip's cryptographic acceleration and offloading hardware and combines cryptographic and other mathematical functions to create a modular and scalable hardware acceleration and assurance engine. Registration without Disclaimer /secured/assets/documents/en/reference-manual/LX2160ASECRM.pdf English documents 6704086 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=LX2160ASECRM LX2160A Security (SEC) Reference Manual /secured/assets/documents/en/reference-manual/LX2160ASECRM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 0 Y N LX2160A Security (SEC) Reference Manual 6.7 MB LX2160ASECRM N 1595230028328718283020 /secured/assets/documents/en/reference-manual/LX2160ADPAA2RM.pdf 2020-06-18 1592476874355717141786 PSP 4 Jun 18, 2020 Reference Manual This document provides information about NXP's second generation Data Path Acceleration Architecture (DPAA2). Registration without Disclaimer /secured/assets/documents/en/reference-manual/LX2160ADPAA2RM.pdf English documents 13931706 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=LX2160ADPAA2RM LX2160A Family Data Path Acceleration Architecture, Second Generation (DPAA2) Low-Level Hardware Reference Manual /secured/assets/documents/en/reference-manual/LX2160ADPAA2RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 0 Y N LX2160A Family Data Path Acceleration Architecture, Second Generation (DPAA2) Low-Level Hardware Reference Manual 13.9 MB LX2160ADPAA2RM N 1592476874355717141786 Supporting Information 2 /docs/en/supporting-information/LX2160A_2120A_2080A-PECI.pdf 2018-08-22 1534961268333709344687 PSP 31 Aug 22, 2018 Supporting Information LX2160A, 2120A, 2080A Family Export Control Information None /docs/en/supporting-information/LX2160A_2120A_2080A-PECI.pdf English documents 90111 None 371282830530968666 2023-06-19 N /docs/en/supporting-information/LX2160A_2120A_2080A-PECI.pdf LX2160A, 2120A, 2080A Family Export Control Information /docs/en/supporting-information/LX2160A_2120A_2080A-PECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1 N N LX2160A, 2120A, 2080A Family Export Control Information 90.1 KB LX2160A_2120A_2080A-PECI N 1534961268333709344687 /docs/en/supporting-information/FSLNISTCAVP.pdf 2016-11-09 1368836090577704535160 PSP 32 Oct 28, 2016 Supporting Information FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. None /docs/en/supporting-information/FSLNISTCAVP.pdf English documents 303546 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1.9 N N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 303.5 KB FSLNISTCAVP N 1368836090577704535160 User Manual 1 /secured/assets/documents/en/user-guide/DPAA2UM.pdf 2020-02-26 1582785451078700466276 PSP 26 Sep 19, 2023 User Manual DPAA2 is a hardware-level networking architecture found on some NXP SoCs. This document provides technical information on this architecture mainly for software developers. Registration without Disclaimer /secured/assets/documents/en/user-guide/DPAA2UM.pdf English documents 5987656 None 309919593431037931 2023-09-21 Y /webapp/Download?colCode=DPAA2UM DPAA2 User Manual /secured/assets/documents/en/user-guide/DPAA2UM.pdf documents 309919593431037931 User Manual N en Extended Y pdf 53 Y N DPAA2 User Manual 6.0 MB DPAA2UM N 1582785451078700466276 White Paper 2 /docs/en/product-brief/EDN-SCULPT-16CORE-PROCESSOR.pdf 2018-06-28 1530198601380706887406 PSP 33 Jun 28, 2018 White Paper HOW TO SCULPT A 16-CORE 2 GHZ PROCESSOR None /docs/en/product-brief/EDN-SCULPT-16CORE-PROCESSOR.pdf English documents 607144 None 918633085541740938 2023-06-19 N /docs/en/product-brief/EDN-SCULPT-16CORE-PROCESSOR.pdf HOW TO SCULPT A 16-CORE 2 GHZ PROCESSOR /docs/en/product-brief/EDN-SCULPT-16CORE-PROCESSOR.pdf documents 918633085541740938 White Paper N en None Y pdf 1.0 N N HOW TO SCULPT A 16-CORE 2 GHZ PROCESSOR 607.1 KB EDN-SCULPT-16CORE-PROCESSOR N 1530198601380706887406 /docs/en/supporting-information/LX2160A-NXP-Biggest-Multicore.pdf 2017-11-09 1510277371621724576420 PSP 34 Nov 9, 2017 White Paper NXP is chasing high-end networking with its newest QorIQ processor, the LX2160A. Sporting 16 Arm<sup>®</sup> Cortex<sup>®</sup>-A72 cores, 100 Gigabit Ethernet, a 16-port Layer 2 switch, and faster acceleration for cryptography and data compres-sion, it will be the company’s largest and fastest multicore embedded processor when it begins production—in mid-2019, by our estimate. None /docs/en/supporting-information/LX2160A-NXP-Biggest-Multicore.pdf English documents 604575 None 918633085541740938 2023-06-19 N /docs/en/supporting-information/LX2160A-NXP-Biggest-Multicore.pdf LX2160A NXP's Biggest Multicore /docs/en/supporting-information/LX2160A-NXP-Biggest-Multicore.pdf documents 918633085541740938 White Paper N en None Y pdf 1 N N LX2160A NXP's Biggest Multicore 604.6 KB LX2160A-NXP-BM N 1510277371621724576420 true Y Products

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