PowerQUICC® III Processor with DDR2, PCI, PCI Express®, Serial RapidIO, SerDes, 1 GB Ethernet, Security | NXP Semiconductors

PowerQUICC® III Processor with DDR2, PCI, PCI Express®, Serial RapidIO, SerDes, 1 GB Ethernet, Security

More

Product Details

Features

  • Secure Communications Architecture leveraging Mocana's Device Security Framework technology
  • Embedded e500 core, scaling up to 1.5 GHz
    • Dual Dispatch super-scaler, 7-stage pipeline design with out-of-order issue and execution
    • 3065 MIPS at 1333 MHz (estimated Dhrystone 2.1)
  • Integrated L1/L2 cache
    • L1 cache -32 KB data and 32 KB instruction cache with line-locking support
    • L2 cache -512 KB (8-way set associative); 512 KB/256 KB/128 KB/64 KB can be used as SRAM
    • L1 and L2 hardware coherency
    • L2 configurable as SRAM, cache or stash cache
  • Integrated DDR memory controller with full ECC support, supporting:
    • 200 MHz clock rate (400 MHz data rate), 64-bit, 2.5V/2.6V I/O, DDR SDRAM
    • 266 MHz clock rate (up to 533 MHz data rate) DDR2 SDRAM
  • Double-precision embedded scalar and vector floating-point APUs
  • Memory management unit (MMU)
  • Integrated security engine supporting DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 encryption algorithms.
  • Multiple PCI interface support
    • 64-bit PCI 2.2 bus controller (up to 66 MHz, 3.3V I/O)
    • 64-bit PCI-X bus controller (up to 133 MHz, 3.3V I/O), or
    • Flexibility to configure two 32-bit PCI controllers
  • Four on-chip triple-speed Ethernet controllers (GMACs) supporting 10- and 100-Mbps, and 1-Gbps Ethernet/802.3 networks with MII, RMII, GMII, RGMII, RTBI and TBI physical interfaces.
    • TCP/IP checksum acceleration
    • Advanced QoS features
  • General-purpose I/O
  • Serial RapidIO and PCI Express high-speed interconnect interfaces, supporting
    • Single x8 PCI Express, or
    • Single x4 PCI Express and single 4x Serial RapidIO
  • On-chip network (OCeaN) switch fabric
  • Integrated four-channel DMA controller
  • Dual I²C interfaces and Dual Universal Asynchronous Receiver/Transmitter (DUART) support
  • Programmable interrupt controller (PIC)
  • General-purpose parallel I/O (GPIO)
  • IEEE 1149.1 JTAG test access port
  • 1.1V core voltage with 3.3V and 2.5V I/O
  • 783-pin FC-BGA package
  • This product is included in NXP product longevity program, with assured supply for a minimum of 10 years after launch

Buy/Parametrics










































































































N true 0 PSPMPC8543Een 51 Application Note Application Note t789 32 Application Note Software Application Note Software t783 4 Data Sheet Data Sheet t520 1 Errata Errata t522 1 Fact Sheet Fact Sheet t523 1 Package Information Package Information t790 1 Reference Manual Reference Manual t877 5 Supporting Information Supporting Information t531 2 White Paper White Paper t530 4 en_US 3 1 2 English This reference manual defines the functionality of the MPC8548E. This device integrates an e500v2&#13;&#10;processor core, based on Power Architecture&#8482; technology, with system logic required for networking, telecommunications, and wireless infrastructure applications. 1120082396246734711219 PSP 14.6 MB None None documents None 1120082396246734711219 /docs/en/reference-manual/MPC8548ERM.pdf 14562038 /docs/en/reference-manual/MPC8548ERM.pdf MPC8548ERM N N 2005-06-30 MPC8548E Reference Manual /docs/en/reference-manual/MPC8548ERM.pdf /docs/en/reference-manual/MPC8548ERM.pdf Reference Manual N Y 500633505221135046 2022-12-07 pdf N en Feb 9, 2007 Reference Manual t877 Reference Manual Reference Manual Y N MPC8548E Reference Manual 2 1 English The MPC8548E networking/telecom processor features an embedded e500 core, targeting up to a 1.5 GHz core operation, an integrated security engine, 64-bit DDR/ DDR2 controller scaling up to 667 MHz data rate, dual 32-bit PCI or 64-bit PCI-X, 4-bit serial RapidIO &#174; fabric technology and 4-bit PCI Express &#174; (or single 8-bit PCI Express 1.0a), local bus I/O interfaces and four Gigabit Ethernet interfaces. 1156359985243719313449 PSP 231.6 KB None None documents None 1156359985243719313449 /docs/en/fact-sheet/MPC8548PQIIIFS.pdf 231567 /docs/en/fact-sheet/MPC8548PQIIIFS.pdf MPC8548PQIIIFS N 2006-08-23 MPC8548E PowerQUICC<sup>&#174;</sup> &#8482; III Processor Family - Fact Sheet /docs/en/fact-sheet/MPC8548PQIIIFS.pdf /docs/en/fact-sheet/MPC8548PQIIIFS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 pdf en Jun 15, 2007 Fact Sheet t523 Fact Sheet Fact Sheet Y N MPC8548E PowerQUICC<sup>&#174;</sup> &#8482; III Processor Family - Fact Sheet 3 10 English MPC8548EEC: This document describes the electrical characteristics of the MPC8548E, MPC8547E, MPC8545E, and MPC8543E. 1184263891554720325592 PSP 1.3 MB None None documents None 1184263891554720325592 /docs/en/data-sheet/MPC8548EEC.pdf 1291312 /docs/en/data-sheet/MPC8548EEC.pdf MPC8548EEC N N 2007-07-12 MPC8548EEC, MPC8548E PowerQUICC<sup>&#174;</sup> III Integrated Processor Hardware Specifications - Data Sheet /docs/en/data-sheet/MPC8548EEC.pdf /docs/en/data-sheet/MPC8548EEC.pdf Data Sheet N Y 980000996212993340 2022-12-07 pdf N en Jun 24, 2014 Data Sheet t520 Data Sheet Data Sheet Y N MPC8548EEC, MPC8548E PowerQUICC<sup>&#174;</sup> III Integrated Processor Hardware Specifications - Data Sheet false en_US en Reference Manual Reference Manual 4 4 1 English This reference manual describes the resources defined for the Power ISA embedded environment. 1319210247754725815434 PSP 10.4 MB Registration without Disclaimer None documents Extended 1319210247754725815434 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 10448185 /secured/assets/documents/en/reference-manual/EREF_RM.pdf EREF_RM documents Y N 2016-10-31 EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /webapp/Download?colCode=EREF_RM /secured/assets/documents/en/reference-manual/EREF_RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jun 26, 2014 500633505221135046 Reference Manual Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 5 1.2 English E500CORER: This errata document describes corrections to the PowerPC &#8482; e500 Core Family Reference Manual, Revision 1. 1152820363245707387417 PSP 117.9 KB None None documents None 1152820363245707387417 /docs/en/reference-manual/e500CORERMAD.pdf 117856 /docs/en/reference-manual/e500CORERMAD.pdf E500CORERMAD documents N N 2016-10-31 E500CORER, Errata to PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/e500CORERMAD.pdf /docs/en/reference-manual/e500CORERMAD.pdf Reference Manual N 500633505221135046 2022-12-07 pdf N en Sep 11, 2012 500633505221135046 Reference Manual N E500CORER, Errata to PowerPC ™ e500 Core Family - Reference Manual 6 2.4 English MPC8548ERMAD, This errata describes corrections to the MPC8548E PowerQUICC<sup>&#174;</sup> III Integrated Host Processor Family Reference Manual, Revision 2. 1129236957432697488892 PSP 813.5 KB None None documents None 1129236957432697488892 /docs/en/reference-manual/MPC8548ERMAD.pdf 813540 /docs/en/reference-manual/MPC8548ERMAD.pdf MPC8548ERMAD documents N N 2005-10-13 MPC8548ERMAD, Errata to MPC8548E PowerQUICC<sup>&#174;</sup> III Integrated Host Processor Family Reference Manual, Rev. 2 /docs/en/reference-manual/MPC8548ERMAD.pdf /docs/en/reference-manual/MPC8548ERMAD.pdf Reference Manual N 500633505221135046 2022-12-07 pdf N en Apr 24, 2012 500633505221135046 Reference Manual Y N MPC8548ERMAD, Errata to MPC8548E PowerQUICC<sup>&#174;</sup> III Integrated Host Processor Family Reference Manual, Rev. 2 7 1 English The primary objective of this user&#8217;s manual is to describe the functionality of the e500 embedded microprocessor core for software and hardware developers. The e500 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the PowerPC architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words in the 64-bit general-purpose registers (GPRs). 111qmdXB PSP 5.7 MB None None documents None 111qmdXB /docs/en/reference-manual/E500CORERM.pdf 5707515 /docs/en/reference-manual/E500CORERM.pdf E500CORERM documents N 2016-10-31 PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/E500CORERM.pdf /docs/en/reference-manual/E500CORERM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf en May 11, 2005 500633505221135046 Reference Manual N PowerPC ™ e500 Core Family - Reference Manual Application Note Application Note 32 8 0 Chinese Reviewing the troubleshoot microcontroller when there is a malfunction module. 1641302649210707506203zh PSP 303.0 KB None None documents None 1641302649210707506203 /docs/zh/application-note/AN13461.pdf 302971 /docs/zh/application-note/AN13461.pdf AN13461 documents N N 2022-01-04 AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note /docs/zh/application-note/AN13461.pdf /docs/zh/application-note/AN13461.pdf Application Note N 645036621402383989 2022-12-07 zh May 9, 2022 645036621402383989 Application Note Y N 恩智浦微控制器故障排除清单 0 English Reviewing the troubleshoot microcontroller when there is a malfunction module. 1641302649210707506203 PSP 303.0 KB None None documents None 1641302649210707506203 /docs/en/application-note/AN13461.pdf 302971 /docs/en/application-note/AN13461.pdf AN13461 documents N N 2022-01-04 AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note /docs/en/application-note/AN13461.pdf /docs/en/application-note/AN13461.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 30, 2021 645036621402383989 Application Note Y N AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note 9 3 English This document is a supplement to the SEC 2/3x reference device driver. 1224778148188710027580 PSP 1.1 MB Registration without Disclaimer None documents Extended 1224778148188710027580 /secured/assets/documents/en/application-note/AN3645.pdf 1147132 /secured/assets/documents/en/application-note/AN3645.pdf AN3645 documents Y N 2016-10-31 SEC 2/3x Descriptor Programmer’s Guide /webapp/Download?colCode=AN3645 /secured/assets/documents/en/application-note/AN3645.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Apr 28, 2017 645036621402383989 Application Note N SEC 2/3x Descriptor Programmer’s Guide 10 2 English Using the Core and System Performance Monitors 1493403864930712885479 PSP 278.3 KB Registration without Disclaimer None documents Extended 1493403864930712885479 /secured/assets/documents/en/application-note/AN3636.pdf 278345 /secured/assets/documents/en/application-note/AN3636.pdf AN3636 documents Y N 2017-04-28 PowerQUICC III Performance Monitors /webapp/Download?colCode=AN3636 /secured/assets/documents/en/application-note/AN3636.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Apr 28, 2017 645036621402383989 Application Note Y N PowerQUICC III Performance Monitors 11 11 English AN2583: This application note provides programming guidelines for the PowerQUICC<sup>&#174;</sup> DDR-SDRAM memory controller and specifically JEDEC-compatible DDR1 SDRAM memories. 1070297961506735248621 PSP 333.2 KB None None documents None 1070297961506735248621 /docs/en/application-note/AN2583.pdf 333170 /docs/en/application-note/AN2583.pdf AN2583 documents N N 2003-12-01 AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note /docs/en/application-note/AN2583.pdf /docs/en/application-note/AN2583.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jul 29, 2014 645036621402383989 Application Note Y N AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note 12 2 English This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. 1363012931515701443659 PSP 269.4 KB None None documents None 1363012931515701443659 /docs/en/application-note/AN4531.pdf 269380 /docs/en/application-note/AN4531.pdf AN4531 documents N N 2016-10-31 AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf /docs/en/application-note/AN4531.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Dec 16, 2013 645036621402383989 Application Note N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 13 Rev. 0 English This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. 1305312143395731535528 PSP 577.2 KB Registration without Disclaimer None documents Extended 1305312143395731535528 /secured/assets/documents/en/application-note/AN4311.pdf 577164 /secured/assets/documents/en/application-note/AN4311.pdf AN4311 documents Y N 2016-10-31 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /webapp/Download?colCode=AN4311 /secured/assets/documents/en/application-note/AN4311.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 13, 2011 645036621402383989 Application Note Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 14 0 English AN3830: This application note provides a practical guide to using Our CodeWarrior IDE to debug hardware. Focusing on PowerQUICC<sup>&#174;</sup> processors, this document covers many of the key features available in the IDE to assist in bring-up and troubleshooting of a new board. 1245429781973738421244 PSP 1.6 MB None None documents None 1245429781973738421244 /docs/en/application-note/AN3830.pdf 1576181 /docs/en/application-note/AN3830.pdf AN3830 documents N 2009-06-19 AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes /docs/en/application-note/AN3830.pdf /docs/en/application-note/AN3830.pdf Application Note N 645036621402383989 2022-12-07 pdf en Feb 1, 2011 645036621402383989 Application Note Y N AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes 15 3 English This document provides recommendations for new designs based on the MPC8548E PowerQUICC&#8482; III family of integrated host communications processors (collectively referred to throughout this document as MPC8548E):&#13;&#10;&#8226; MPC8548E&#13;&#10;&#8226; MPC8548&#13;&#10;&#8226; MPC8547E&#13;&#10;&#8226; MPC8545E&#13;&#10;&#8226; MPC8545&#13;&#10;&#8226; MPC8543E&#13;&#10;&#8226; MPC8543&#13;&#10;This document may also be useful in debugging newly designed systems by highlighting those aspects of a desi 1214506196840728648963 PSP 269.9 KB None None documents None 1214506196840728648963 /docs/en/application-note/AN3640.pdf 269877 /docs/en/application-note/AN3640.pdf AN3640 documents N 2008-06-26 MPC8548E PowerQUICC<sup>&#174;</sup>&#8482; III Family Bring-Up Guide /docs/en/application-note/AN3640.pdf /docs/en/application-note/AN3640.pdf Application Note N 645036621402383989 2022-12-07 pdf en Aug 1, 2010 645036621402383989 Application Note Y N MPC8548E PowerQUICC<sup>&#174;</sup>&#8482; III Family Bring-Up Guide 16 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939 /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors 17 1 English This application note explains the contents of the leader device tree in a multicore Hypervisor implementation used to allocate system resources to the individual partitions.&#13;&#10;Additionally, it describes the contents of the individual device trees that each partition uses for local allocation of those resources. 1225213465876727613770 PSP 828.9 KB None None documents None 1225213465876727613770 /docs/en/application-note/AN3649.pdf 828938 /docs/en/application-note/AN3649.pdf AN3649 documents N N 2016-10-31 Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations /docs/en/application-note/AN3649.pdf /docs/en/application-note/AN3649.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Apr 19, 2010 645036621402383989 Application Note Y N Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations 18 0 English AN4064: This document explains how to enable and utilize 36-bit physical addressing. It describes the 36-bit capabilities of the e600 and e500v2, and later processor families. Addressing and memory management in a computer system is a difficult topic that is largely beyond the scope of this document. This section explains some of the basic concepts that are essential to understand in order to develop system-level software that utilizes 36-bit physical addressing. 1269842191514722596708 PSP 576.8 KB None None documents None 1269842191514722596708 /docs/en/application-note/AN4064.pdf 576818 /docs/en/application-note/AN4064.pdf AN4064 documents N 2016-10-31 AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes /docs/en/application-note/AN4064.pdf /docs/en/application-note/AN4064.pdf Application Note N 645036621402383989 2022-12-07 pdf en Mar 28, 2010 645036621402383989 Application Note N AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes 19 1 English This application note describes basic jitter terminology and the aspects pertaining to the SYSCLK clock design requirements. 1264143083962735811350 PSP 514.4 KB None None documents None 1264143083962735811350 /docs/en/application-note/AN4056.pdf 514364 /docs/en/application-note/AN4056.pdf AN4056 documents N 2016-10-31 Understanding SYSCLK Jitter /docs/en/application-note/AN4056.pdf /docs/en/application-note/AN4056.pdf Application Note N 645036621402383989 2022-12-07 pdf en Feb 18, 2010 645036621402383989 Application Note N Understanding SYSCLK Jitter 20 0 English AN4026SW.zip /secured/assets/documents/en/application-note-software/AN4026SW.zip /webapp/Download?colCode=AN4026SW&appType=license&docLang=en A common use of the QUICC Engine block is to establish an HDLC communication path over a TDM interface, such as a T1 or E1 link. This application note describes the various sub-blocks used in the QUICC Engine communications engine for this application, discusses how the sub-blocks interoperate with each other, describes how to initialize them for the HDLC communication path, and provides a software demonstration of HDLC mode via a TDM interface using on-chip loopback. 1260992898773711434436 PSP 718.0 KB None None documents None 1260992898773711434436 /docs/en/application-note/AN4026.pdf 718019 /docs/en/application-note/AN4026.pdf AN4026 documents N 2009-12-17 Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC /docs/en/application-note/AN4026.pdf /docs/en/application-note/AN4026.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 17, 2009 645036621402383989 Application Note N Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC 21 0 English High-level data link control (HDLC) is widely used in the telecommunications and networking industries. NXP&#8217;s PowerQUICC&#8482; communications processors have extensive support for HDLC protocol through the communications processor module (CPM) and QUICC Engine&#8482; technologies.&#13;&#10;&#13;&#10;This application note explains how NXP&#8217;s existing&#13;&#10;PowerQUICC communications processors use the CPM and QUICC Engine technologies to support the HDLC protocol and provides HDLC e 1258066893562722616236 PSP 496.6 KB None None documents None 1258066893562722616236 /docs/en/application-note/AN3966.pdf 496625 /docs/en/application-note/AN3966.pdf AN3966 documents N 2016-10-31 PowerQUICC™ HDLC Support and Example Code /docs/en/application-note/AN3966.pdf /docs/en/application-note/AN3966.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 10, 2009 645036621402383989 Application Note N PowerQUICC™ HDLC Support and Example Code 22 2 English NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. 1213738938672737755656 PSP 495.3 KB None None documents None 1213738938672737755656 /docs/en/application-note/AN3638.pdf 495318 /docs/en/application-note/AN3638.pdf AN3638 documents N N 2016-10-31 The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf /docs/en/application-note/AN3638.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Oct 26, 2009 645036621402383989 Application Note N The SystemID Format for Power Architecture™ Development Systems 23 0 English This document is an overview of how to configure&#13;&#10;PowerQUICC<sup>&#174;</sup> III and QorIQ<sup>&#174;</sup> P1xx/P2xx devices to boot from serial RapidIO&#8482; or PCI Express&#8482; with no additional boot flash/EEPROM. 1256145464773713684480 PSP 543.1 KB Registration without Disclaimer None documents Extended 1256145464773713684480 /secured/assets/documents/en/application-note/AN3646.pdf 543108 /secured/assets/documents/en/application-note/AN3646.pdf AN3646 documents Y N 2016-10-31 Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx /webapp/Download?colCode=AN3646 /secured/assets/documents/en/application-note/AN3646.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Oct 21, 2009 645036621402383989 Application Note N Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx 24 2 English AN2810SW.zip /secured/assets/documents/en/application-note-software/AN2810SW.zip /webapp/Download?colCode=AN2810SW&appType=license&docLang=en This application note describes how to effectively program and use the universal programmable machine (UPM) in the PowerQUICC<sup>&#174;</sup> line of communication processors through NXP&#8217;s UPM software tools. 1104253596524716967025 PSP 807.8 KB None None documents None 1104253596524716967025 /docs/en/application-note/AN2810.pdf 807775 /docs/en/application-note/AN2810.pdf AN2810 documents N 2005-01-03 PowerQUICC<sup>&#174;</sup>&#8482; UPM Configuration /docs/en/application-note/AN2810.pdf /docs/en/application-note/AN2810.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 20, 2009 645036621402383989 Application Note Y N PowerQUICC<sup>&#174;</sup>&#8482; UPM Configuration 25 0 English This application note explains configuration&#13;&#10;requirements to assist users to successfully program and set up this interface type. It also compares SGMII to other gigabit Ethernet standards and interfaces. 1244236817778728476903 PSP 692.4 KB Registration without Disclaimer None documents Extended 1244236817778728476903 /secured/assets/documents/en/application-note/AN3869.pdf 692438 /secured/assets/documents/en/application-note/AN3869.pdf AN3869 documents Y N 2016-10-31 Implementing SGMII Interfaces on the PowerQUICC™ III /webapp/Download?colCode=AN3869 /secured/assets/documents/en/application-note/AN3869.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 5, 2009 645036621402383989 Application Note N Implementing SGMII Interfaces on the PowerQUICC™ III 26 0 English This application note explains the procedures to utilize the extra FC (Flow Control) credits for PCI Express inbound posted memory write transactions, which is currently a hidden feature for the Power QUICC III&#8482; devices. 1243968993550696784184 PSP 476.0 KB None None documents None 1243968993550696784184 /docs/en/application-note/AN3781.pdf 476033 /docs/en/application-note/AN3781.pdf AN3781 documents N 2010-05-11 Utilizing Extra FC Credits for PCI Express Inbound Posted Memory Write Transactions in PowerQUICC III&#8482; Devices /docs/en/application-note/AN3781.pdf /docs/en/application-note/AN3781.pdf Application Note N 645036621402383989 2022-12-07 pdf en Jun 2, 2009 645036621402383989 Application Note N Utilizing Extra FC Credits for PCI Express Inbound Posted Memory Write Transactions in PowerQUICC III&#8482; Devices 27 5 English This document explains how the frequency divider to calculate the SCL speed of the I2C interface is determined for the MPC824x, MPC83xx, MPC85xx, and MPC86xx devices. 1119553728324723212395 PSP 611.4 KB Registration without Disclaimer None documents Extended 1119553728324723212395 /secured/assets/documents/en/application-note/AN2919.pdf 611358 /secured/assets/documents/en/application-note/AN2919.pdf AN2919 documents Y N 2016-10-31 Determining the I2C Frequency Divider Ratio for SCL /webapp/Download?colCode=AN2919 /secured/assets/documents/en/application-note/AN2919.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Dec 31, 2008 645036621402383989 Application Note N Determining the I2C Frequency Divider Ratio for SCL 28 5.0 English This document expands on the description of the double data rate (DDR2) memory controller programmable registers described in the reference manuals for PowerQUICC processors. The corresponding material in the reference manual defines the function of each field in the programmable registers. This application note focuses when and why to select certain configurations of the bits and fields in the DDR2 registers to achieve efficient DDR programming. 1176147669904707686124 PSP 535.3 KB None None documents None 1176147669904707686124 /docs/en/application-note/AN3369.pdf 535277 /docs/en/application-note/AN3369.pdf AN3369 documents N 2007-04-09 PowerQUICC<sup>&#174;</sup> DDR2 SDRAM Controller Register Setting Considerations /docs/en/application-note/AN3369.pdf /docs/en/application-note/AN3369.pdf Application Note N 645036621402383989 2022-12-07 pdf en Sep 11, 2008 645036621402383989 Application Note Y N PowerQUICC<sup>&#174;</sup> DDR2 SDRAM Controller Register Setting Considerations 29 0 English This application note provides an overview and specific strategies for cache coherency and potential performance impacts in the PowerQUICC<sup>&#174;</sup> II Pro and PowerQUICC III families. It focuses on data coherency and potential system issues, as well as some concerns associated with having multiple DMA devices. It also discusses the specific steps and interdependencies required to implement hardware enforced cache coherency. 1198270786976715604383 PSP 547.7 KB None None documents None 1198270786976715604383 /docs/en/application-note/AN3544.pdf 547694 /docs/en/application-note/AN3544.pdf AN3544 documents N 2016-10-31 PowerQUICC™ Data Cache Coherency /docs/en/application-note/AN3544.pdf /docs/en/application-note/AN3544.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 21, 2007 645036621402383989 Application Note N PowerQUICC™ Data Cache Coherency 30 1 English This document describes aspects of memory synchronization and cache coherency requirements for NXP&#8217;s PowerQUICC<sup>&#174;</sup>&#8482; III product family. Coherency and synchronization need be considered, both for data and instructions, when initializing memory or moving memory contents from one location to another. 1191253168152709402147 PSP 189.0 KB None None documents None 1191253168152709402147 /docs/en/application-note/AN3441.pdf 188954 /docs/en/application-note/AN3441.pdf AN3441 documents N 2016-10-31 Coherency and Synchronization Requirements for PowerQUICC™ III /docs/en/application-note/AN3441.pdf /docs/en/application-note/AN3441.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 17, 2007 645036621402383989 Application Note N Coherency and Synchronization Requirements for PowerQUICC™ III 31 0 English This application note provides an introduction to the error correcting code (ECC) technology as well as an aid to initialization and error recovery on Our PowerQUICC<sup>&#174;</sup> III family of processors. 1196228463425717224884 PSP 573.0 KB None None documents None 1196228463425717224884 /docs/en/application-note/AN3532.pdf 572952 /docs/en/application-note/AN3532.pdf AN3532 documents N 2016-10-31 Error Correction and Error Handling on PowerQUICC (TM) III Processors /docs/en/application-note/AN3532.pdf /docs/en/application-note/AN3532.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 27, 2007 645036621402383989 Application Note N Error Correction and Error Handling on PowerQUICC (TM) III Processors 32 0 English AN3445: This application note outlines general, high-level, architectural differences between the e300 and e500 family processors. The e300 family (which are based on the original 603 design) was designed to the original PowerPC architecture definition. The e500v1 and e500v2 processors are designed to what was originally the PowerPC Book E architecture and NXP?s embedded implementation standards (EIS). 1194389310604697206738 PSP 935.0 KB None None documents None 1194389310604697206738 /docs/en/application-note/AN3445.pdf 934951 /docs/en/application-note/AN3445.pdf AN3445 documents N 2016-10-31 AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3445.pdf /docs/en/application-note/AN3445.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 31, 2007 645036621402383989 Application Note N AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes 33 0 English AN3531: This application note outlines general, high-level, architectural differences between the e600 and e500 family processors. Is intended as a general guideline for programmers and system designers who are assessing the efforts required in migrating to e500-based devices. 1194389312415718217914 PSP 961.6 KB None None documents None 1194389312415718217914 /docs/en/application-note/AN3531.pdf 961596 /docs/en/application-note/AN3531.pdf AN3531 documents N N 2016-10-31 AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3531.pdf /docs/en/application-note/AN3531.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Oct 31, 2007 645036621402383989 Application Note N AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes 34 2 English These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. 1128961595061725581551 PSP 619.7 KB None None documents None 1128961595061725581551 /docs/en/application-note/AN2910.pdf 619650 /docs/en/application-note/AN2910.pdf AN2910 documents N 2016-10-31 Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf /docs/en/application-note/AN2910.pdf Application Note N 645036621402383989 2022-12-07 pdf en Mar 27, 2007 645036621402383989 Application Note N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces 35 0 English This document reviews the use of Ethernet and RapidIO as a system interconnect fabric, comparing them against the requirements for such fabrics. Quantitative analysis is presented where possible. 1171553356793694633748 PSP 784.2 KB None None documents None 1171553356793694633748 /docs/en/application-note/AN3088.pdf 784203 /docs/en/application-note/AN3088.pdf AN3088 documents N 2007-02-15 System Interconnect Fabrics: Ethernet Versus RapidIO /docs/en/application-note/AN3088.pdf /docs/en/application-note/AN3088.pdf Application Note N 645036621402383989 2022-12-07 pdf en Feb 15, 2007 645036621402383989 Application Note Y N System Interconnect Fabrics: Ethernet Versus RapidIO 36 0 English This document summarizes the features of the MPC8548E Linux BSP and provides instructions on how to install the LTIB-based BSP on a host development system, run LTIB to build target images needed for deployment, deploy the built image to the MPC8548CDS board, and boot Linux on the MPC8548CDS board. 1165002784485714600692 PSP 506.4 KB None None documents None 1165002784485714600692 /docs/en/application-note/AN3094.pdf 506389 /docs/en/application-note/AN3094.pdf AN3094 documents N 2006-12-01 Linux Board Support Package (BSP) Targeting the MPC8548E CDS System /docs/en/application-note/AN3094.pdf /docs/en/application-note/AN3094.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 1, 2006 645036621402383989 Application Note Y N Linux Board Support Package (BSP) Targeting the MPC8548E CDS System 37 0 English This document provides guidelines for basic use of the PowerQUICC<sup>&#174;</sup> III serial RapidIO interface. 1133538491299733535557 PSP 1.1 MB None None documents None 1133538491299733535557 /docs/en/application-note/AN2932.pdf 1052512 /docs/en/application-note/AN2932.pdf AN2932 documents N 2005-12-02 Serial RapidIO Bring-Up Procedure on PowerQUICC<sup>&#174;</sup> III /docs/en/application-note/AN2932.pdf /docs/en/application-note/AN2932.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 2, 2005 645036621402383989 Application Note Y N Serial RapidIO Bring-Up Procedure on PowerQUICC<sup>&#174;</sup> III 38 0 English This application note is provided to assist those engineers wishing to use the serial RapidIO message unit on the PowerQUICC<sup>&#174;</sup>&#8482; III. It summarizes the features and uses of the RapidIO messaging unit (including data messages, doorbell messages and inbound port-writes) and provides example code. These extracted code segments are part of a simple application, written to run on top of U-Boot, to prove the functionality of the messaging unit. 1127154752940725970276 PSP 530.6 KB None None documents None 1127154752940725970276 /docs/en/application-note/AN2923.pdf 530575 /docs/en/application-note/AN2923.pdf AN2923 documents N 2005-09-19 Using the Serial RapidIO Messaging Unit on PowerQUICC<sup>&#174;</sup> III /docs/en/application-note/AN2923.pdf /docs/en/application-note/AN2923.pdf Application Note N 645036621402383989 2022-12-07 pdf en Sep 19, 2005 645036621402383989 Application Note Y N Using the Serial RapidIO Messaging Unit on PowerQUICC<sup>&#174;</sup> III 39 1 English Application note 1096906262959704348247 PSP 211.8 KB None None documents None 1096906262959704348247 /docs/en/application-note/AN2663.pdf 211783 /docs/en/application-note/AN2663.pdf AN2663 documents N 2004-10-04 A Cache Primer /docs/en/application-note/AN2663.pdf /docs/en/application-note/AN2663.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 4, 2004 645036621402383989 Application Note Y N A Cache Primer Application Note Software Application Note Software 4 40 0 English 1258066894053701788655 PSP 330.9 KB Registration With Click-Thru Software Licensing Agreement 1395958162559706127527 documents Extended 1258066894053701788655 /secured/assets/documents/en/application-note-software/AN3966SW.zip 330857 /secured/assets/documents/en/application-note-software/AN3966SW.zip AN3966SW documents Y N 2016-10-31 Software to accompany application note AN3966 /webapp/Download?colCode=AN3966SW&appType=license /secured/assets/documents/en/application-note-software/AN3966SW.zip Application Note Software N 789425793691620447 2022-12-07 zip Y en Nov 10, 2009 789425793691620447 Application Note Software N Software to accompany application note AN3966 41 0 English This application note addresses a common challenge encountered during circuit board testing with some of the newer NXP microprocessors. It is common practice for board testing houses to test for shorts on the power rails by measuring the resistance from a power rail to the ground rail. In older technologies, this is a reasonable approach. However, this application note explains why this approach can be problematic when used with devices in newer technologies. 1181767584945705509512 PSP 163.7 KB None None documents None 1181767584945705509512 /docs/en/application-note-software/AN3372.pdf 163681 /docs/en/application-note-software/AN3372.pdf AN3372 documents N 2016-10-31 Challenges in Testing for Power Rail Shorts with New Technologies /docs/en/application-note-software/AN3372.pdf /docs/en/application-note-software/AN3372.pdf Application Note Software N 789425793691620447 2022-12-07 pdf en Jun 13, 2007 789425793691620447 Application Note Software N Challenges in Testing for Power Rail Shorts with New Technologies 42 1 English To help expedite Power Architecture board bringup, this application note describes how to port the CodeWarrior target initialization file from the NXP MPC8555CDS development system to a custom development system. The target initialization file offers many benefits, such as the ability to debug a system before there is working code and a working system. 1177528532487728727257 PSP 955.3 KB None None documents None 1177528532487728727257 /docs/en/application-note-software/AN3366.pdf 955336 /docs/en/application-note-software/AN3366.pdf AN3366 documents N 2007-04-25 Simplifying Board Bringup: Porting a CodeWarrior<sup>&#174;</sup> Initialization File to Your System /docs/en/application-note-software/AN3366.pdf /docs/en/application-note-software/AN3366.pdf Application Note Software N 789425793691620447 2022-12-07 pdf en May 22, 2007 789425793691620447 Application Note Software D N Simplifying Board Bringup: Porting a CodeWarrior<sup>&#174;</sup> Initialization File to Your System 43 2 English AN2810, PowerQUICC<sup>&#174;</sup> UPM Configuration, PowerQUICC, Universal Programmable Machine, Configuration, Application Note 1113503860374718430905 PSP 5.6 KB Registration With Click-Thru Software Licensing Agreement 1395958162559706127527 documents Extended 1113503860374718430905 /secured/assets/documents/en/application-note-software/AN2810SW.zip 5555 /secured/assets/documents/en/application-note-software/AN2810SW.zip AN2810SW documents Y N 2005-04-14 AN2810 Supporting Files /webapp/Download?colCode=AN2810SW&appType=license /secured/assets/documents/en/application-note-software/AN2810SW.zip Application Note Software N 789425793691620447 2022-12-07 zip Y en Aug 15, 2006 789425793691620447 Application Note Software N AN2810 Supporting Files Errata Errata 1 44 6 English This document details all known silicon errata for MPC8548E, MPC8547E, MPC8545E, and MPC8543E PowerQUICC<sup>&#174;</sup> III devices. 1229542205212724144347 PSP 521.1 KB None None documents None 1229542205212724144347 /docs/en/errata/MPC8548ECE.pdf 521093 /docs/en/errata/MPC8548ECE.pdf MPC8548ECE documents N N 2008-12-17 MPC8548E Chip Errata /docs/en/errata/MPC8548ECE.pdf /docs/en/errata/MPC8548ECE.pdf Errata N 155452329886410597 2022-12-07 pdf N en Jun 29, 2012 155452329886410597 Errata Y N MPC8548E Chip Errata Package Information Package Information 1 45 1 English This document is a presentation on understanding the FC-PBGA package. 1273780789511716723050 PSP 5.2 MB None None documents None 1273780789511716723050 /docs/en/package-information/FC-PBGAPRES.pdf 5219387 /docs/en/package-information/FC-PBGAPRES.pdf FC-PBGAPRES documents N N 2016-10-31 Flip Chip Plastic Ball Grid Array (FC-PBGA) Presentation /docs/en/package-information/FC-PBGAPRES.pdf /docs/en/package-information/FC-PBGAPRES.pdf Package Information N 302435339416912908 2022-12-07 pdf N en Jul 8, 2015 302435339416912908 Package Information N Flip Chip Plastic Ball Grid Array (FC-PBGA) Presentation Supporting Information Supporting Information 2 46 1.9 English FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. 1368836090577704535160 PSP 303.5 KB None None documents None 1368836090577704535160 /docs/en/supporting-information/FSLNISTCAVP.pdf 303546 /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP documents N N 2016-11-09 FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf /docs/en/supporting-information/FSLNISTCAVP.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 28, 2016 371282830530968666 Supporting Information Y N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 47 1 English 1475686551849736498831 PSP 87.7 KB None None documents None 1475686551849736498831 /docs/en/supporting-information/MPC8543_45-PECI.pdf 87692 /docs/en/supporting-information/MPC8543_45-PECI.pdf MPC8543_45-PECI documents N N 2016-11-09 MPC8543 _45 family Customer Export Control Information /docs/en/supporting-information/MPC8543_45-PECI.pdf /docs/en/supporting-information/MPC8543_45-PECI.pdf Supporting Information N 371282830530968666 2023-06-19 pdf N en Oct 5, 2016 371282830530968666 Supporting Information Y N MPC8543 _45 family Customer Export Control Information White Paper White Paper 4 48 3 English Network security protocols and applications use a variety of cryptographic algorithms to achieve these high-level goals. Because cryptography is computationally intensive, hardware acceleration is highly desirable when cryptographic algorithms are frequent system functions. 1227561595497709456436 PSP 580.1 KB Registration without Disclaimer None documents Extended 1227561595497709456436 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf 580121 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf CRYPTOWP documents Y N 2016-10-31 Understanding Cryptographic Performance /webapp/Download?colCode=CRYPTOWP /secured/assets/documents/en/white-paper/CRYPTOWP.pdf White Paper N 918633085541740938 2022-12-07 pdf Y en Aug 15, 2008 918633085541740938 White Paper Y N Understanding Cryptographic Performance 49 0 English The focus of this white paper is to provide the end user with high level design considerations and/or trade-offs associated with migrating from SDRAM to DDR SDRAM-based designs. 1208376896761708228520 PSP 735.3 KB None None documents None 1208376896761708228520 /docs/en/white-paper/DDRSDRAMWP.pdf 735286 /docs/en/white-paper/DDRSDRAMWP.pdf DDRSDRAMWP documents N N 2016-10-31 Comparison of DDRx and SDRAM /docs/en/white-paper/DDRSDRAMWP.pdf /docs/en/white-paper/DDRSDRAMWP.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Apr 16, 2008 918633085541740938 White Paper Y N Comparison of DDRx and SDRAM 50 1 English White Paper 1109024327078700240135 PSP 246.1 KB None None documents None 1109024327078700240135 /docs/en/white-paper/NANDFLASHWP.pdf 246130 /docs/en/white-paper/NANDFLASHWP.pdf NANDFLASHWP documents N N 2016-10-31 How to Interface the PowerQUICC II Pro and PowerQUICC III Local Bus Controller to NAND Flash /docs/en/white-paper/NANDFLASHWP.pdf /docs/en/white-paper/NANDFLASHWP.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Oct 24, 2005 918633085541740938 White Paper Y N How to Interface the PowerQUICC II Pro and PowerQUICC III Local Bus Controller to NAND Flash 51 0 English White Paper 1108068301263725831691 PSP 74.0 KB None None documents None 1108068301263725831691 /docs/en/white-paper/PublicKeyPerfWP.pdf 73984 /docs/en/white-paper/PublicKeyPerfWP.pdf PUBLICKEYPERFWP documents N N 2016-10-31 Understanding Public-Key Performance /docs/en/white-paper/PublicKeyPerfWP.pdf /docs/en/white-paper/PublicKeyPerfWP.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Feb 10, 2005 918633085541740938 White Paper Y N Understanding Public-Key Performance false 0 MPC8543E downloads en true 1 Y PSP Application Note 32 /docs/en/application-note/AN13461.pdf 2022-01-04 1641302649210707506203 PSP 8 Nov 30, 2021 Application Note Reviewing the troubleshoot microcontroller when there is a malfunction module. None /docs/en/application-note/AN13461.pdf English documents 302971 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN13461.pdf AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note /docs/en/application-note/AN13461.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note 303.0 KB AN13461 N 1641302649210707506203 /secured/assets/documents/en/application-note/AN3645.pdf 2016-10-31 1224778148188710027580 PSP 9 Apr 28, 2017 Application Note This document is a supplement to the SEC 2/3x reference device driver. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3645.pdf English documents 1147132 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3645 SEC 2/3x Descriptor Programmer’s Guide /secured/assets/documents/en/application-note/AN3645.pdf documents 645036621402383989 Application Note N en Extended pdf 3 Y N SEC 2/3x Descriptor Programmer’s Guide 1.1 MB AN3645 N 1224778148188710027580 /secured/assets/documents/en/application-note/AN3636.pdf 2017-04-28 1493403864930712885479 PSP 10 Apr 28, 2017 Application Note Using the Core and System Performance Monitors Registration without Disclaimer /secured/assets/documents/en/application-note/AN3636.pdf English documents 278345 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3636 PowerQUICC III Performance Monitors /secured/assets/documents/en/application-note/AN3636.pdf documents 645036621402383989 Application Note N en Extended Y pdf 2 Y N PowerQUICC III Performance Monitors 278.3 KB AN3636 N 1493403864930712885479 /docs/en/application-note/AN2583.pdf 2003-12-01 1070297961506735248621 PSP 11 Jul 29, 2014 Application Note AN2583: This application note provides programming guidelines for the PowerQUICC<sup>&#174;</sup> DDR-SDRAM memory controller and specifically JEDEC-compatible DDR1 SDRAM memories. None /docs/en/application-note/AN2583.pdf English documents 333170 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN2583.pdf AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note /docs/en/application-note/AN2583.pdf documents 645036621402383989 Application Note N en None Y pdf 11 N N AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note 333.2 KB AN2583 N 1070297961506735248621 /docs/en/application-note/AN4531.pdf 2016-10-31 1363012931515701443659 PSP 12 Dec 16, 2013 Application Note This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. None /docs/en/application-note/AN4531.pdf English documents 269380 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4531.pdf AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf documents 645036621402383989 Application Note N en None pdf 2 N N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 269.4 KB AN4531 N 1363012931515701443659 /secured/assets/documents/en/application-note/AN4311.pdf 2016-10-31 1305312143395731535528 PSP 13 May 13, 2011 Application Note This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4311.pdf English documents 577164 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4311 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /secured/assets/documents/en/application-note/AN4311.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev. 0 Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 577.2 KB AN4311 N 1305312143395731535528 /docs/en/application-note/AN3830.pdf 2009-06-19 1245429781973738421244 PSP 14 Feb 1, 2011 Application Note AN3830: This application note provides a practical guide to using Our CodeWarrior IDE to debug hardware. Focusing on PowerQUICC<sup>&#174;</sup> processors, this document covers many of the key features available in the IDE to assist in bring-up and troubleshooting of a new board. None /docs/en/application-note/AN3830.pdf English documents 1576181 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3830.pdf AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes /docs/en/application-note/AN3830.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes 1.6 MB AN3830 N 1245429781973738421244 /docs/en/application-note/AN3640.pdf 2008-06-26 1214506196840728648963 PSP 15 Aug 1, 2010 Application Note This document provides recommendations for new designs based on the MPC8548E PowerQUICC&#8482; III family of integrated host communications processors (collectively referred to throughout this document as MPC8548E):&#13;&#10;&#8226; MPC8548E&#13;&#10;&#8226; MPC8548&#13;&#10;&#8226; MPC8547E&#13;&#10;&#8226; MPC8545E&#13;&#10;&#8226; MPC8545&#13;&#10;&#8226; MPC8543E&#13;&#10;&#8226; MPC8543&#13;&#10;This document may also be useful in debugging newly designed systems by highlighting those aspects of a desi None /docs/en/application-note/AN3640.pdf English documents 269877 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3640.pdf MPC8548E PowerQUICC<sup>&#174;</sup>&#8482; III Family Bring-Up Guide /docs/en/application-note/AN3640.pdf documents 645036621402383989 Application Note N en None Y pdf 3 N MPC8548E PowerQUICC<sup>&#174;</sup>&#8482; III Family Bring-Up Guide 269.9 KB AN3640 N 1214506196840728648963 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 16 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939 DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 /docs/en/application-note/AN3649.pdf 2016-10-31 1225213465876727613770 PSP 17 Apr 19, 2010 Application Note This application note explains the contents of the leader device tree in a multicore Hypervisor implementation used to allocate system resources to the individual partitions.&#13;&#10;Additionally, it describes the contents of the individual device trees that each partition uses for local allocation of those resources. None /docs/en/application-note/AN3649.pdf English documents 828938 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3649.pdf Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations /docs/en/application-note/AN3649.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations 828.9 KB AN3649 N 1225213465876727613770 /docs/en/application-note/AN4064.pdf 2016-10-31 1269842191514722596708 PSP 18 Mar 28, 2010 Application Note AN4064: This document explains how to enable and utilize 36-bit physical addressing. It describes the 36-bit capabilities of the e600 and e500v2, and later processor families. Addressing and memory management in a computer system is a difficult topic that is largely beyond the scope of this document. This section explains some of the basic concepts that are essential to understand in order to develop system-level software that utilizes 36-bit physical addressing. None /docs/en/application-note/AN4064.pdf English documents 576818 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4064.pdf AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes /docs/en/application-note/AN4064.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes 576.8 KB AN4064 N 1269842191514722596708 /docs/en/application-note/AN4056.pdf 2016-10-31 1264143083962735811350 PSP 19 Feb 18, 2010 Application Note This application note describes basic jitter terminology and the aspects pertaining to the SYSCLK clock design requirements. None /docs/en/application-note/AN4056.pdf English documents 514364 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4056.pdf Understanding SYSCLK Jitter /docs/en/application-note/AN4056.pdf documents 645036621402383989 Application Note N en None pdf 1 N Understanding SYSCLK Jitter 514.4 KB AN4056 N 1264143083962735811350 /docs/en/application-note/AN4026.pdf 2009-12-17 1260992898773711434436 PSP 20 Dec 17, 2009 Application Note A common use of the QUICC Engine block is to establish an HDLC communication path over a TDM interface, such as a T1 or E1 link. This application note describes the various sub-blocks used in the QUICC Engine communications engine for this application, discusses how the sub-blocks interoperate with each other, describes how to initialize them for the HDLC communication path, and provides a software demonstration of HDLC mode via a TDM interface using on-chip loopback. None /docs/en/application-note/AN4026.pdf English documents 718019 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4026.pdf Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC /docs/en/application-note/AN4026.pdf documents 645036621402383989 Application Note N en None pdf 0 N Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC 718.0 KB AN4026 N 1260992898773711434436 /docs/en/application-note/AN3966.pdf 2016-10-31 1258066893562722616236 PSP 21 Nov 10, 2009 Application Note High-level data link control (HDLC) is widely used in the telecommunications and networking industries. NXP&#8217;s PowerQUICC&#8482; communications processors have extensive support for HDLC protocol through the communications processor module (CPM) and QUICC Engine&#8482; technologies.&#13;&#10;&#13;&#10;This application note explains how NXP&#8217;s existing&#13;&#10;PowerQUICC communications processors use the CPM and QUICC Engine technologies to support the HDLC protocol and provides HDLC e None /docs/en/application-note/AN3966.pdf English documents 496625 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3966.pdf PowerQUICC™ HDLC Support and Example Code /docs/en/application-note/AN3966.pdf documents 645036621402383989 Application Note N en None pdf 0 N PowerQUICC™ HDLC Support and Example Code 496.6 KB AN3966 N 1258066893562722616236 /docs/en/application-note/AN3638.pdf 2016-10-31 1213738938672737755656 PSP 22 Oct 26, 2009 Application Note NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. None /docs/en/application-note/AN3638.pdf English documents 495318 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3638.pdf The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf documents 645036621402383989 Application Note N en None pdf 2 N N The SystemID Format for Power Architecture™ Development Systems 495.3 KB AN3638 N 1213738938672737755656 /secured/assets/documents/en/application-note/AN3646.pdf 2016-10-31 1256145464773713684480 PSP 23 Oct 21, 2009 Application Note This document is an overview of how to configure&#13;&#10;PowerQUICC<sup>&#174;</sup> III and QorIQ<sup>&#174;</sup> P1xx/P2xx devices to boot from serial RapidIO&#8482; or PCI Express&#8482; with no additional boot flash/EEPROM. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3646.pdf English documents 543108 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3646 Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx /secured/assets/documents/en/application-note/AN3646.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx 543.1 KB AN3646 N 1256145464773713684480 /docs/en/application-note/AN2810.pdf 2005-01-03 1104253596524716967025 PSP 24 Oct 20, 2009 Application Note This application note describes how to effectively program and use the universal programmable machine (UPM) in the PowerQUICC<sup>&#174;</sup> line of communication processors through NXP&#8217;s UPM software tools. None /docs/en/application-note/AN2810.pdf English documents 807775 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2810.pdf PowerQUICC<sup>&#174;</sup>&#8482; UPM Configuration /docs/en/application-note/AN2810.pdf documents 645036621402383989 Application Note N en None Y pdf 2 N PowerQUICC<sup>&#174;</sup>&#8482; UPM Configuration 807.8 KB AN2810 N 1104253596524716967025 /secured/assets/documents/en/application-note/AN3869.pdf 2016-10-31 1244236817778728476903 PSP 25 Jun 5, 2009 Application Note This application note explains configuration&#13;&#10;requirements to assist users to successfully program and set up this interface type. It also compares SGMII to other gigabit Ethernet standards and interfaces. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3869.pdf English documents 692438 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3869 Implementing SGMII Interfaces on the PowerQUICC™ III /secured/assets/documents/en/application-note/AN3869.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N Implementing SGMII Interfaces on the PowerQUICC™ III 692.4 KB AN3869 N 1244236817778728476903 /docs/en/application-note/AN3781.pdf 2010-05-11 1243968993550696784184 PSP 26 Jun 2, 2009 Application Note This application note explains the procedures to utilize the extra FC (Flow Control) credits for PCI Express inbound posted memory write transactions, which is currently a hidden feature for the Power QUICC III&#8482; devices. None /docs/en/application-note/AN3781.pdf English documents 476033 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3781.pdf Utilizing Extra FC Credits for PCI Express Inbound Posted Memory Write Transactions in PowerQUICC III&#8482; Devices /docs/en/application-note/AN3781.pdf documents 645036621402383989 Application Note N en None pdf 0 N Utilizing Extra FC Credits for PCI Express Inbound Posted Memory Write Transactions in PowerQUICC III&#8482; Devices 476.0 KB AN3781 N 1243968993550696784184 /secured/assets/documents/en/application-note/AN2919.pdf 2016-10-31 1119553728324723212395 PSP 27 Dec 31, 2008 Application Note This document explains how the frequency divider to calculate the SCL speed of the I2C interface is determined for the MPC824x, MPC83xx, MPC85xx, and MPC86xx devices. Registration without Disclaimer /secured/assets/documents/en/application-note/AN2919.pdf English documents 611358 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN2919 Determining the I2C Frequency Divider Ratio for SCL /secured/assets/documents/en/application-note/AN2919.pdf documents 645036621402383989 Application Note N en Extended pdf 5 Y N Determining the I2C Frequency Divider Ratio for SCL 611.4 KB AN2919 N 1119553728324723212395 /docs/en/application-note/AN3369.pdf 2007-04-09 1176147669904707686124 PSP 28 Sep 11, 2008 Application Note This document expands on the description of the double data rate (DDR2) memory controller programmable registers described in the reference manuals for PowerQUICC processors. The corresponding material in the reference manual defines the function of each field in the programmable registers. This application note focuses when and why to select certain configurations of the bits and fields in the DDR2 registers to achieve efficient DDR programming. None /docs/en/application-note/AN3369.pdf English documents 535277 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3369.pdf PowerQUICC<sup>&#174;</sup> DDR2 SDRAM Controller Register Setting Considerations /docs/en/application-note/AN3369.pdf documents 645036621402383989 Application Note N en None Y pdf 5.0 N PowerQUICC<sup>&#174;</sup> DDR2 SDRAM Controller Register Setting Considerations 535.3 KB AN3369 N 1176147669904707686124 /docs/en/application-note/AN3544.pdf 2016-10-31 1198270786976715604383 PSP 29 Dec 21, 2007 Application Note This application note provides an overview and specific strategies for cache coherency and potential performance impacts in the PowerQUICC<sup>&#174;</sup> II Pro and PowerQUICC III families. It focuses on data coherency and potential system issues, as well as some concerns associated with having multiple DMA devices. It also discusses the specific steps and interdependencies required to implement hardware enforced cache coherency. None /docs/en/application-note/AN3544.pdf English documents 547694 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3544.pdf PowerQUICC™ Data Cache Coherency /docs/en/application-note/AN3544.pdf documents 645036621402383989 Application Note N en None pdf 0 N PowerQUICC™ Data Cache Coherency 547.7 KB AN3544 N 1198270786976715604383 /docs/en/application-note/AN3441.pdf 2016-10-31 1191253168152709402147 PSP 30 Dec 17, 2007 Application Note This document describes aspects of memory synchronization and cache coherency requirements for NXP&#8217;s PowerQUICC<sup>&#174;</sup>&#8482; III product family. Coherency and synchronization need be considered, both for data and instructions, when initializing memory or moving memory contents from one location to another. None /docs/en/application-note/AN3441.pdf English documents 188954 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3441.pdf Coherency and Synchronization Requirements for PowerQUICC™ III /docs/en/application-note/AN3441.pdf documents 645036621402383989 Application Note N en None pdf 1 N Coherency and Synchronization Requirements for PowerQUICC™ III 189.0 KB AN3441 N 1191253168152709402147 /docs/en/application-note/AN3532.pdf 2016-10-31 1196228463425717224884 PSP 31 Nov 27, 2007 Application Note This application note provides an introduction to the error correcting code (ECC) technology as well as an aid to initialization and error recovery on Our PowerQUICC<sup>&#174;</sup> III family of processors. None /docs/en/application-note/AN3532.pdf English documents 572952 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3532.pdf Error Correction and Error Handling on PowerQUICC (TM) III Processors /docs/en/application-note/AN3532.pdf documents 645036621402383989 Application Note N en None pdf 0 N Error Correction and Error Handling on PowerQUICC (TM) III Processors 573.0 KB AN3532 N 1196228463425717224884 /docs/en/application-note/AN3445.pdf 2016-10-31 1194389310604697206738 PSP 32 Oct 31, 2007 Application Note AN3445: This application note outlines general, high-level, architectural differences between the e300 and e500 family processors. The e300 family (which are based on the original 603 design) was designed to the original PowerPC architecture definition. The e500v1 and e500v2 processors are designed to what was originally the PowerPC Book E architecture and NXP?s embedded implementation standards (EIS). None /docs/en/application-note/AN3445.pdf English documents 934951 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3445.pdf AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3445.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes 935.0 KB AN3445 N 1194389310604697206738 /docs/en/application-note/AN3531.pdf 2016-10-31 1194389312415718217914 PSP 33 Oct 31, 2007 Application Note AN3531: This application note outlines general, high-level, architectural differences between the e600 and e500 family processors. Is intended as a general guideline for programmers and system designers who are assessing the efforts required in migrating to e500-based devices. None /docs/en/application-note/AN3531.pdf English documents 961596 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3531.pdf AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3531.pdf documents 645036621402383989 Application Note N en None pdf 0 N N AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes 961.6 KB AN3531 N 1194389312415718217914 /docs/en/application-note/AN2910.pdf 2016-10-31 1128961595061725581551 PSP 34 Mar 27, 2007 Application Note These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. None /docs/en/application-note/AN2910.pdf English documents 619650 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2910.pdf Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf documents 645036621402383989 Application Note N en None pdf 2 N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces 619.7 KB AN2910 N 1128961595061725581551 /docs/en/application-note/AN3088.pdf 2007-02-15 1171553356793694633748 PSP 35 Feb 15, 2007 Application Note This document reviews the use of Ethernet and RapidIO as a system interconnect fabric, comparing them against the requirements for such fabrics. Quantitative analysis is presented where possible. None /docs/en/application-note/AN3088.pdf English documents 784203 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3088.pdf System Interconnect Fabrics: Ethernet Versus RapidIO /docs/en/application-note/AN3088.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N System Interconnect Fabrics: Ethernet Versus RapidIO 784.2 KB AN3088 N 1171553356793694633748 /docs/en/application-note/AN3094.pdf 2006-12-01 1165002784485714600692 PSP 36 Dec 1, 2006 Application Note This document summarizes the features of the MPC8548E Linux BSP and provides instructions on how to install the LTIB-based BSP on a host development system, run LTIB to build target images needed for deployment, deploy the built image to the MPC8548CDS board, and boot Linux on the MPC8548CDS board. None /docs/en/application-note/AN3094.pdf English documents 506389 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3094.pdf Linux Board Support Package (BSP) Targeting the MPC8548E CDS System /docs/en/application-note/AN3094.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N Linux Board Support Package (BSP) Targeting the MPC8548E CDS System 506.4 KB AN3094 N 1165002784485714600692 /docs/en/application-note/AN2932.pdf 2005-12-02 1133538491299733535557 PSP 37 Dec 2, 2005 Application Note This document provides guidelines for basic use of the PowerQUICC<sup>&#174;</sup> III serial RapidIO interface. None /docs/en/application-note/AN2932.pdf English documents 1052512 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2932.pdf Serial RapidIO Bring-Up Procedure on PowerQUICC<sup>&#174;</sup> III /docs/en/application-note/AN2932.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N Serial RapidIO Bring-Up Procedure on PowerQUICC<sup>&#174;</sup> III 1.1 MB AN2932 N 1133538491299733535557 /docs/en/application-note/AN2923.pdf 2005-09-19 1127154752940725970276 PSP 38 Sep 19, 2005 Application Note This application note is provided to assist those engineers wishing to use the serial RapidIO message unit on the PowerQUICC<sup>&#174;</sup>&#8482; III. It summarizes the features and uses of the RapidIO messaging unit (including data messages, doorbell messages and inbound port-writes) and provides example code. These extracted code segments are part of a simple application, written to run on top of U-Boot, to prove the functionality of the messaging unit. None /docs/en/application-note/AN2923.pdf English documents 530575 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2923.pdf Using the Serial RapidIO Messaging Unit on PowerQUICC<sup>&#174;</sup> III /docs/en/application-note/AN2923.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N Using the Serial RapidIO Messaging Unit on PowerQUICC<sup>&#174;</sup> III 530.6 KB AN2923 N 1127154752940725970276 /docs/en/application-note/AN2663.pdf 2004-10-04 1096906262959704348247 PSP 39 Oct 4, 2004 Application Note Application note None /docs/en/application-note/AN2663.pdf English documents 211783 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2663.pdf A Cache Primer /docs/en/application-note/AN2663.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N A Cache Primer 211.8 KB AN2663 N 1096906262959704348247 Application Note Software 4 /secured/assets/documents/en/application-note-software/AN3966SW.zip 2016-10-31 1258066894053701788655 PSP 40 Nov 10, 2009 Application Note Software Registration With Click-Thru Software Licensing Agreement /secured/assets/documents/en/application-note-software/AN3966SW.zip English documents 330857 1395958162559706127527 789425793691620447 2022-12-07 Y /webapp/Download?colCode=AN3966SW&appType=license Software to accompany application note AN3966 /secured/assets/documents/en/application-note-software/AN3966SW.zip documents 789425793691620447 Application Note Software N en Extended zip 0 Y N Software to accompany application note AN3966 330.9 KB AN3966SW N 1258066894053701788655 /docs/en/application-note-software/AN3372.pdf 2016-10-31 1181767584945705509512 PSP 41 Jun 13, 2007 Application Note Software This application note addresses a common challenge encountered during circuit board testing with some of the newer NXP microprocessors. It is common practice for board testing houses to test for shorts on the power rails by measuring the resistance from a power rail to the ground rail. In older technologies, this is a reasonable approach. However, this application note explains why this approach can be problematic when used with devices in newer technologies. None /docs/en/application-note-software/AN3372.pdf English documents 163681 None 789425793691620447 2022-12-07 /docs/en/application-note-software/AN3372.pdf Challenges in Testing for Power Rail Shorts with New Technologies /docs/en/application-note-software/AN3372.pdf documents 789425793691620447 Application Note Software N en None pdf 0 N Challenges in Testing for Power Rail Shorts with New Technologies 163.7 KB AN3372 N 1181767584945705509512 /docs/en/application-note-software/AN3366.pdf 2007-04-25 1177528532487728727257 PSP 42 May 22, 2007 Application Note Software To help expedite Power Architecture board bringup, this application note describes how to port the CodeWarrior target initialization file from the NXP MPC8555CDS development system to a custom development system. The target initialization file offers many benefits, such as the ability to debug a system before there is working code and a working system. None /docs/en/application-note-software/AN3366.pdf English documents 955336 None 789425793691620447 2022-12-07 /docs/en/application-note-software/AN3366.pdf Simplifying Board Bringup: Porting a CodeWarrior<sup>&#174;</sup> Initialization File to Your System /docs/en/application-note-software/AN3366.pdf documents 789425793691620447 Application Note Software N en None D pdf 1 N Simplifying Board Bringup: Porting a CodeWarrior<sup>&#174;</sup> Initialization File to Your System 955.3 KB AN3366 N 1177528532487728727257 /secured/assets/documents/en/application-note-software/AN2810SW.zip 2005-04-14 1113503860374718430905 PSP 43 Aug 15, 2006 Application Note Software AN2810, PowerQUICC<sup>&#174;</sup> UPM Configuration, PowerQUICC, Universal Programmable Machine, Configuration, Application Note Registration With Click-Thru Software Licensing Agreement /secured/assets/documents/en/application-note-software/AN2810SW.zip English documents 5555 1395958162559706127527 789425793691620447 2022-12-07 Y /webapp/Download?colCode=AN2810SW&appType=license AN2810 Supporting Files /secured/assets/documents/en/application-note-software/AN2810SW.zip documents 789425793691620447 Application Note Software N en Extended zip 2 Y N AN2810 Supporting Files 5.6 KB AN2810SW N 1113503860374718430905 Data Sheet 1 /docs/en/data-sheet/MPC8548EEC.pdf 2007-07-12 1184263891554720325592 PSP 3 Jun 24, 2014 Data Sheet Data Sheet MPC8548EEC: This document describes the electrical characteristics of the MPC8548E, MPC8547E, MPC8545E, and MPC8543E. None /docs/en/data-sheet/MPC8548EEC.pdf English 1291312 None Data Sheet 2022-12-07 N /docs/en/data-sheet/MPC8548EEC.pdf MPC8548EEC, MPC8548E PowerQUICC<sup>&#174;</sup> III Integrated Processor Hardware Specifications - Data Sheet /docs/en/data-sheet/MPC8548EEC.pdf documents 980000996212993340 Data Sheet N Y en None Y t520 pdf 10 N N MPC8548EEC, MPC8548E PowerQUICC<sup>&#174;</sup> III Integrated Processor Hardware Specifications - Data Sheet 1.3 MB MPC8548EEC N 1184263891554720325592 Errata 1 /docs/en/errata/MPC8548ECE.pdf 2008-12-17 1229542205212724144347 PSP 44 Jun 29, 2012 Errata This document details all known silicon errata for MPC8548E, MPC8547E, MPC8545E, and MPC8543E PowerQUICC<sup>&#174;</sup> III devices. None /docs/en/errata/MPC8548ECE.pdf English documents 521093 None 155452329886410597 2022-12-07 N /docs/en/errata/MPC8548ECE.pdf MPC8548E Chip Errata /docs/en/errata/MPC8548ECE.pdf documents 155452329886410597 Errata N en None Y pdf 6 N N MPC8548E Chip Errata 521.1 KB MPC8548ECE N 1229542205212724144347 Fact Sheet 1 /docs/en/fact-sheet/MPC8548PQIIIFS.pdf 2006-08-23 1156359985243719313449 PSP 2 Jun 15, 2007 Fact Sheet Fact Sheet The MPC8548E networking/telecom processor features an embedded e500 core, targeting up to a 1.5 GHz core operation, an integrated security engine, 64-bit DDR/ DDR2 controller scaling up to 667 MHz data rate, dual 32-bit PCI or 64-bit PCI-X, 4-bit serial RapidIO &#174; fabric technology and 4-bit PCI Express &#174; (or single 8-bit PCI Express 1.0a), local bus I/O interfaces and four Gigabit Ethernet interfaces. None /docs/en/fact-sheet/MPC8548PQIIIFS.pdf English 231567 None Fact Sheet 2022-12-07 /docs/en/fact-sheet/MPC8548PQIIIFS.pdf MPC8548E PowerQUICC<sup>&#174;</sup> &#8482; III Processor Family - Fact Sheet /docs/en/fact-sheet/MPC8548PQIIIFS.pdf documents 736675474163315314 Fact Sheet N Y en None Y t523 pdf 1 N MPC8548E PowerQUICC<sup>&#174;</sup> &#8482; III Processor Family - Fact Sheet 231.6 KB MPC8548PQIIIFS N 1156359985243719313449 Package Information 1 /docs/en/package-information/FC-PBGAPRES.pdf 2016-10-31 1273780789511716723050 PSP 45 Jul 8, 2015 Package Information This document is a presentation on understanding the FC-PBGA package. None /docs/en/package-information/FC-PBGAPRES.pdf English documents 5219387 None 302435339416912908 2022-12-07 N /docs/en/package-information/FC-PBGAPRES.pdf Flip Chip Plastic Ball Grid Array (FC-PBGA) Presentation /docs/en/package-information/FC-PBGAPRES.pdf documents 302435339416912908 Package Information N en None pdf 1 N N Flip Chip Plastic Ball Grid Array (FC-PBGA) Presentation 5.2 MB FC-PBGAPRES N 1273780789511716723050 Reference Manual 5 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 2016-10-31 1319210247754725815434 PSP 4 Jun 26, 2014 Reference Manual This reference manual describes the resources defined for the Power ISA embedded environment. Registration without Disclaimer /secured/assets/documents/en/reference-manual/EREF_RM.pdf English documents 10448185 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=EREF_RM EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /secured/assets/documents/en/reference-manual/EREF_RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 1 Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 10.4 MB EREF_RM N 1319210247754725815434 /docs/en/reference-manual/e500CORERMAD.pdf 2016-10-31 1152820363245707387417 PSP 5 Sep 11, 2012 Reference Manual E500CORER: This errata document describes corrections to the PowerPC &#8482; e500 Core Family Reference Manual, Revision 1. None /docs/en/reference-manual/e500CORERMAD.pdf English documents 117856 None 500633505221135046 2022-12-07 N /docs/en/reference-manual/e500CORERMAD.pdf E500CORER, Errata to PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/e500CORERMAD.pdf documents 500633505221135046 Reference Manual N en None pdf 1.2 N N E500CORER, Errata to PowerPC ™ e500 Core Family - Reference Manual 117.9 KB E500CORERMAD N 1152820363245707387417 /docs/en/reference-manual/MPC8548ERMAD.pdf 2005-10-13 1129236957432697488892 PSP 6 Apr 24, 2012 Reference Manual MPC8548ERMAD, This errata describes corrections to the MPC8548E PowerQUICC<sup>&#174;</sup> III Integrated Host Processor Family Reference Manual, Revision 2. None /docs/en/reference-manual/MPC8548ERMAD.pdf English documents 813540 None 500633505221135046 2022-12-07 N /docs/en/reference-manual/MPC8548ERMAD.pdf MPC8548ERMAD, Errata to MPC8548E PowerQUICC<sup>&#174;</sup> III Integrated Host Processor Family Reference Manual, Rev. 2 /docs/en/reference-manual/MPC8548ERMAD.pdf documents 500633505221135046 Reference Manual N en None Y pdf 2.4 N N MPC8548ERMAD, Errata to MPC8548E PowerQUICC<sup>&#174;</sup> III Integrated Host Processor Family Reference Manual, Rev. 2 813.5 KB MPC8548ERMAD N 1129236957432697488892 /docs/en/reference-manual/E500CORERM.pdf 2016-10-31 111qmdXB PSP 7 May 11, 2005 Reference Manual The primary objective of this user&#8217;s manual is to describe the functionality of the e500 embedded microprocessor core for software and hardware developers. The e500 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the PowerPC architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words in the 64-bit general-purpose registers (GPRs). None /docs/en/reference-manual/E500CORERM.pdf English documents 5707515 None 500633505221135046 2022-12-07 /docs/en/reference-manual/E500CORERM.pdf PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/E500CORERM.pdf documents 500633505221135046 Reference Manual N en None pdf 1 N PowerPC ™ e500 Core Family - Reference Manual 5.7 MB E500CORERM N 111qmdXB /docs/en/reference-manual/MPC8548ERM.pdf 2005-06-30 1120082396246734711219 PSP 1 Feb 9, 2007 Reference Manual Reference Manual This reference manual defines the functionality of the MPC8548E. This device integrates an e500v2&#13;&#10;processor core, based on Power Architecture&#8482; technology, with system logic required for networking, telecommunications, and wireless infrastructure applications. None /docs/en/reference-manual/MPC8548ERM.pdf English 14562038 None Reference Manual 2022-12-07 N /docs/en/reference-manual/MPC8548ERM.pdf MPC8548E Reference Manual /docs/en/reference-manual/MPC8548ERM.pdf documents 500633505221135046 Reference Manual N Y en None Y t877 pdf 2 N N MPC8548E Reference Manual 14.6 MB MPC8548ERM N 1120082396246734711219 Supporting Information 2 /docs/en/supporting-information/FSLNISTCAVP.pdf 2016-11-09 1368836090577704535160 PSP 46 Oct 28, 2016 Supporting Information FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. None /docs/en/supporting-information/FSLNISTCAVP.pdf English documents 303546 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1.9 N N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 303.5 KB FSLNISTCAVP N 1368836090577704535160 /docs/en/supporting-information/MPC8543_45-PECI.pdf 2016-11-09 1475686551849736498831 PSP 47 Oct 5, 2016 Supporting Information None /docs/en/supporting-information/MPC8543_45-PECI.pdf English documents 87692 None 371282830530968666 2023-06-19 N /docs/en/supporting-information/MPC8543_45-PECI.pdf MPC8543 _45 family Customer Export Control Information /docs/en/supporting-information/MPC8543_45-PECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1 N N MPC8543 _45 family Customer Export Control Information 87.7 KB MPC8543_45-PECI N 1475686551849736498831 White Paper 4 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf 2016-10-31 1227561595497709456436 PSP 48 Aug 15, 2008 White Paper Network security protocols and applications use a variety of cryptographic algorithms to achieve these high-level goals. Because cryptography is computationally intensive, hardware acceleration is highly desirable when cryptographic algorithms are frequent system functions. Registration without Disclaimer /secured/assets/documents/en/white-paper/CRYPTOWP.pdf English documents 580121 None 918633085541740938 2022-12-07 Y /webapp/Download?colCode=CRYPTOWP Understanding Cryptographic Performance /secured/assets/documents/en/white-paper/CRYPTOWP.pdf documents 918633085541740938 White Paper N en Extended Y pdf 3 Y N Understanding Cryptographic Performance 580.1 KB CRYPTOWP N 1227561595497709456436 /docs/en/white-paper/DDRSDRAMWP.pdf 2016-10-31 1208376896761708228520 PSP 49 Apr 16, 2008 White Paper The focus of this white paper is to provide the end user with high level design considerations and/or trade-offs associated with migrating from SDRAM to DDR SDRAM-based designs. None /docs/en/white-paper/DDRSDRAMWP.pdf English documents 735286 None 918633085541740938 2023-06-19 N /docs/en/white-paper/DDRSDRAMWP.pdf Comparison of DDRx and SDRAM /docs/en/white-paper/DDRSDRAMWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N N Comparison of DDRx and SDRAM 735.3 KB DDRSDRAMWP N 1208376896761708228520 /docs/en/white-paper/NANDFLASHWP.pdf 2016-10-31 1109024327078700240135 PSP 50 Oct 24, 2005 White Paper White Paper None /docs/en/white-paper/NANDFLASHWP.pdf English documents 246130 None 918633085541740938 2023-06-19 N /docs/en/white-paper/NANDFLASHWP.pdf How to Interface the PowerQUICC II Pro and PowerQUICC III Local Bus Controller to NAND Flash /docs/en/white-paper/NANDFLASHWP.pdf documents 918633085541740938 White Paper N en None Y pdf 1 N N How to Interface the PowerQUICC II Pro and PowerQUICC III Local Bus Controller to NAND Flash 246.1 KB NANDFLASHWP N 1109024327078700240135 /docs/en/white-paper/PublicKeyPerfWP.pdf 2016-10-31 1108068301263725831691 PSP 51 Feb 10, 2005 White Paper White Paper None /docs/en/white-paper/PublicKeyPerfWP.pdf English documents 73984 None 918633085541740938 2023-06-19 N /docs/en/white-paper/PublicKeyPerfWP.pdf Understanding Public-Key Performance /docs/en/white-paper/PublicKeyPerfWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N N Understanding Public-Key Performance 74.0 KB PUBLICKEYPERFWP N 1108068301263725831691 true Y Products

Documentation

Quick reference to our documentation types.

1-10 of 51 documents

Compact List

Application Note (32)
Show All

Design Files

Hardware

Quick reference to our board types.

3 hardware offerings

Software

Quick reference to our software types.

3 software files

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

1-5 of 7 engineering services

Show All

To find additional partner offerings that support this product, visit our Partner Marketplace.

Training

1-5 of 6 trainings

Show All

To find additional partner offerings that support this product, visit our Partner Marketplace.

Support

What do you need help with?