Low-Power PowerQUICC® II Pro Processor with DDR2, TDM, PCI, PCI Express, SATA, 1 GB Ethernet, Security, USB | NXP Semiconductors

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Low-Power PowerQUICC® II Pro Processor with DDR2, TDM, PCI, PCI Express, SATA, 1 GB Ethernet, Security, USB

MPC8315E Not Recommended for New Designs

Increased Internet broadcast and downloads for personal and premium content are driving a need for a secure highly integrated platform for multimedia distribution within the home. The MPC8315E provides a high-performance Power Architecture® e300 core up to 400 MHz with 16K I/D L1 cache and integrated x2 serial ATA controllers that help reduce overall BOM cost. The system-on-chip (SoC) also includes two Gigabit Ethernet® controllers for network connectivity, two x1 PCI Express® lanes, TDM interface for VoIP, high-speed USB 2.0 with PHY integrated and security engine for encryption algorithm offload. The MPC8315E, based in 90 nm process technology, provides high integration that simplifies board design and provides a cost-effective solution for critical applications such as network attached storage.

Block Diagram

Freescale PowerQUICC MPC8315E Communications Processor Block Diagram

PowerQUICC<sup>&#174;</sup> MPC8315E Communications Processor Block Diagram
Get diagram PDF

Features

  • Core: e300
  • CPU speed: up to 400 MHz
  • L1 cache: 16 KB I/D
  • Memory controller: 16/32-bit DDR/2 up to 266 MHz
  • Local bus: 16-bit w/NAND boot support
  • PCI: 1-32 bit up to 66 MHz (2.3)
  • PCI Express: 2-x1
  • SATA: 2x1 SATA 2.0 w/PHY
  • Ethernet: 2-10/100/1000 RGMII, (R)MII, RTBI, SGMII
  • USB 2.0: one host or device w/PHY
  • TDM: yes
  • Security: MPC8315E version only
  • UART: dual
  • I²C: single
  • Serial peripheral interface: yes
  • Interrupt controller: yes
  • Package: TEPBGA II
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch

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N true 0 PSPMPC8315Een 29 Application Note Application Note t789 14 Application Note Software Application Note Software t783 2 Brochure Brochure t518 1 Data Sheet Data Sheet t520 1 Errata Errata t522 1 Fact Sheet Fact Sheet t523 3 Product Brief Product Brief t532 1 Reference Manual Reference Manual t877 2 Supporting Information Supporting Information t531 2 White Paper White Paper t530 2 en_US 4 1 3 English The MPC8315E communications processor&#13;&#10;family enables a wide range of feature-rich&#13;&#10;applications that make the digital home&#13;&#10;experience easier, richer and safer. 1189477170939723836600 PSP 232.2 KB None None documents None 1189477170939723836600 /docs/en/fact-sheet/MPC8315EFS.pdf 232152 /docs/en/fact-sheet/MPC8315EFS.pdf MPC8315EFS N 2007-09-11 MPC8315E Fact Sheet /docs/en/fact-sheet/MPC8315EFS.pdf /docs/en/fact-sheet/MPC8315EFS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 pdf en Apr 1, 2009 Fact Sheet t523 Fact Sheet Fact Sheet Y N MPC8315E Fact Sheet 2 2 English This reference manual defines the functionality of the MPC8315E. It is written from the perspective of the MPC8315E, which is the superset device, and unless otherwise noted, the information applies also to the MPC8315, MPC8314E, and MPC8314. Note that the MPC8315 and MPC8314 do not support a security engine. Also, the MPC8314E and MPC8314 do not support dual SATA controllers. 1189648881727718440864 PSP 12.8 MB None None documents None 1189648881727718440864 /docs/en/reference-manual/MPC8315ERM.pdf 12834772 /docs/en/reference-manual/MPC8315ERM.pdf MPC8315ERM N 2007-09-12 MPC8315E Reference Manual /docs/en/reference-manual/MPC8315ERM.pdf /docs/en/reference-manual/MPC8315ERM.pdf Reference Manual N Y 500633505221135046 2022-12-07 pdf en Jun 29, 2010 Reference Manual t877 Reference Manual Reference Manual Y N MPC8315E Reference Manual 3 0 English This document provides an overview of the MPC8315E PowerQUICC<sup>&#174;</sup> II Pro processor features, including a block diagram showing the major functional components. 1190032659021723573365 PSP 519.8 KB None None documents None 1190032659021723573365 /docs/en/product-brief/MPC8315EPB.pdf 519772 /docs/en/product-brief/MPC8315EPB.pdf MPC8315EPB N 2007-09-17 MPC8315E Product Brief /docs/en/product-brief/MPC8315EPB.pdf /docs/en/product-brief/MPC8315EPB.pdf Product Brief N Y 899114358132306053 2022-12-07 pdf en Sep 14, 2007 Product Brief t532 Product Brief Product Brief Y N MPC8315E Product Brief 4 2 English This document provides an overview of the MPC8315E PowerQUICC<sup>&#174;</sup>&#8482; II Pro processor features, including a block diagram showing the major functional components. 1241818921035699995918 PSP 676.9 KB None None documents None 1241818921035699995918 /docs/en/data-sheet/MPC8315EEC.pdf 676915 /docs/en/data-sheet/MPC8315EEC.pdf MPC8315EEC N N 2009-05-10 MPC8315E PowerQUICC<sup>&#174;</sup> II Pro Processor Hardware Specifications /docs/en/data-sheet/MPC8315EEC.pdf /docs/en/data-sheet/MPC8315EEC.pdf Data Sheet N Y 980000996212993340 2022-12-07 pdf N en Nov 23, 2011 Data Sheet t520 Data Sheet Data Sheet Y N MPC8315E PowerQUICC<sup>&#174;</sup> II Pro Processor Hardware Specifications false en_US en Reference Manual Reference Manual 1 5 2.1 English This errata describes corrections to the MPC8315E PowerQUICC<sup>&#174;</sup>&#8482; II Pro Integrated Host Processor&#13;&#10;Family Reference Manual, Revision 2. 1207167761981697706467 PSP 509.1 KB None None documents None 1207167761981697706467 /docs/en/reference-manual/MPC8315ERMAD.pdf 509070 /docs/en/reference-manual/MPC8315ERMAD.pdf MPC8315ERMAD documents N 2008-04-04 Errata to MPC8315E PowerQUICC<sup>&#174;</sup>&#8482; II Pro Integrated Host Processor Family Reference Manual, Rev. 1 /docs/en/reference-manual/MPC8315ERMAD.pdf /docs/en/reference-manual/MPC8315ERMAD.pdf Reference Manual N 500633505221135046 2022-12-07 pdf en Sep 20, 2010 500633505221135046 Reference Manual Y N Errata to MPC8315E PowerQUICC<sup>&#174;</sup>&#8482; II Pro Integrated Host Processor Family Reference Manual, Rev. 1 Application Note Application Note 14 6 0 Chinese Reviewing the troubleshoot microcontroller when there is a malfunction module. 1641302649210707506203zh PSP 303.0 KB None None documents None 1641302649210707506203 /docs/zh/application-note/AN13461.pdf 302971 /docs/zh/application-note/AN13461.pdf AN13461 documents N N 2022-01-04 AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note /docs/zh/application-note/AN13461.pdf /docs/zh/application-note/AN13461.pdf Application Note N 645036621402383989 2022-12-07 zh May 9, 2022 645036621402383989 Application Note Y N 恩智浦微控制器故障排除清单 0 English Reviewing the troubleshoot microcontroller when there is a malfunction module. 1641302649210707506203 PSP 303.0 KB None None documents None 1641302649210707506203 /docs/en/application-note/AN13461.pdf 302971 /docs/en/application-note/AN13461.pdf AN13461 documents N N 2022-01-04 AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note /docs/en/application-note/AN13461.pdf /docs/en/application-note/AN13461.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 30, 2021 645036621402383989 Application Note Y N AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note 7 3 English This document is a supplement to the SEC 2/3x reference device driver. 1224778148188710027580 PSP 1.1 MB Registration without Disclaimer None documents Extended 1224778148188710027580 /secured/assets/documents/en/application-note/AN3645.pdf 1147132 /secured/assets/documents/en/application-note/AN3645.pdf AN3645 documents Y N 2016-10-31 SEC 2/3x Descriptor Programmer’s Guide /webapp/Download?colCode=AN3645 /secured/assets/documents/en/application-note/AN3645.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Apr 28, 2017 645036621402383989 Application Note N SEC 2/3x Descriptor Programmer’s Guide 8 11 English AN2583: This application note provides programming guidelines for the PowerQUICC<sup>&#174;</sup> DDR-SDRAM memory controller and specifically JEDEC-compatible DDR1 SDRAM memories. 1070297961506735248621 PSP 333.2 KB None None documents None 1070297961506735248621 /docs/en/application-note/AN2583.pdf 333170 /docs/en/application-note/AN2583.pdf AN2583 documents N N 2003-12-01 AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note /docs/en/application-note/AN2583.pdf /docs/en/application-note/AN2583.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jul 29, 2014 645036621402383989 Application Note Y N AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note 9 1 English This application note describes the generally recommended connections for the new designs based on the NXP MPC8315E and MPC8315 processors. 1239732833133697944315 PSP 325.4 KB None None documents None 1239732833133697944315 /docs/en/application-note/AN3438.pdf 325357 /docs/en/application-note/AN3438.pdf AN3438 documents N N 2009-04-14 Design Checklist for PowerQUICC<sup>&#174;</sup>&#8482; II Pro MPC8315E Processor /docs/en/application-note/AN3438.pdf /docs/en/application-note/AN3438.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Feb 16, 2012 645036621402383989 Application Note Y N Design Checklist for PowerQUICC<sup>&#174;</sup>&#8482; II Pro MPC8315E Processor 10 Rev. 0 English This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. 1305312143395731535528 PSP 577.2 KB Registration without Disclaimer None documents Extended 1305312143395731535528 /secured/assets/documents/en/application-note/AN4311.pdf 577164 /secured/assets/documents/en/application-note/AN4311.pdf AN4311 documents Y N 2016-10-31 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /webapp/Download?colCode=AN4311 /secured/assets/documents/en/application-note/AN4311.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 13, 2011 645036621402383989 Application Note Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 11 0 English AN3830: This application note provides a practical guide to using Our CodeWarrior IDE to debug hardware. Focusing on PowerQUICC<sup>&#174;</sup> processors, this document covers many of the key features available in the IDE to assist in bring-up and troubleshooting of a new board. 1245429781973738421244 PSP 1.6 MB None None documents None 1245429781973738421244 /docs/en/application-note/AN3830.pdf 1576181 /docs/en/application-note/AN3830.pdf AN3830 documents N 2009-06-19 AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes /docs/en/application-note/AN3830.pdf /docs/en/application-note/AN3830.pdf Application Note N 645036621402383989 2022-12-07 pdf en Feb 1, 2011 645036621402383989 Application Note Y N AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes 12 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939 /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors 13 0 English AN4026SW.zip /secured/assets/documents/en/application-note-software/AN4026SW.zip /webapp/Download?colCode=AN4026SW&appType=license&docLang=en A common use of the QUICC Engine block is to establish an HDLC communication path over a TDM interface, such as a T1 or E1 link. This application note describes the various sub-blocks used in the QUICC Engine communications engine for this application, discusses how the sub-blocks interoperate with each other, describes how to initialize them for the HDLC communication path, and provides a software demonstration of HDLC mode via a TDM interface using on-chip loopback. 1260992898773711434436 PSP 718.0 KB None None documents None 1260992898773711434436 /docs/en/application-note/AN4026.pdf 718019 /docs/en/application-note/AN4026.pdf AN4026 documents N 2009-12-17 Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC /docs/en/application-note/AN4026.pdf /docs/en/application-note/AN4026.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 17, 2009 645036621402383989 Application Note N Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC 14 0 English High-level data link control (HDLC) is widely used in the telecommunications and networking industries. NXP&#8217;s PowerQUICC&#8482; communications processors have extensive support for HDLC protocol through the communications processor module (CPM) and QUICC Engine&#8482; technologies.&#13;&#10;&#13;&#10;This application note explains how NXP&#8217;s existing&#13;&#10;PowerQUICC communications processors use the CPM and QUICC Engine technologies to support the HDLC protocol and provides HDLC e 1258066893562722616236 PSP 496.6 KB None None documents None 1258066893562722616236 /docs/en/application-note/AN3966.pdf 496625 /docs/en/application-note/AN3966.pdf AN3966 documents N 2016-10-31 PowerQUICC™ HDLC Support and Example Code /docs/en/application-note/AN3966.pdf /docs/en/application-note/AN3966.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 10, 2009 645036621402383989 Application Note N PowerQUICC™ HDLC Support and Example Code 15 0 English This application note provides an overview and specific strategies for cache coherency and potential performance impacts in the PowerQUICC<sup>&#174;</sup> II Pro and PowerQUICC III families. It focuses on data coherency and potential system issues, as well as some concerns associated with having multiple DMA devices. It also discusses the specific steps and interdependencies required to implement hardware enforced cache coherency. 1198270786976715604383 PSP 547.7 KB None None documents None 1198270786976715604383 /docs/en/application-note/AN3544.pdf 547694 /docs/en/application-note/AN3544.pdf AN3544 documents N 2016-10-31 PowerQUICC™ Data Cache Coherency /docs/en/application-note/AN3544.pdf /docs/en/application-note/AN3544.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 21, 2007 645036621402383989 Application Note N PowerQUICC™ Data Cache Coherency 16 0 English AN3538SW.zip /docs/en/application-note-software/AN3538SW.zip /docs/en/application-note-software/AN3538SW.zip This application note explains how to configure the memory controller to use ECC and how to use some of its test capabilities to validate correct ECC operation for the PowerQUICC<sup>&#174;</sup> II Pro family. 1197315617339724591437 PSP 460.6 KB None None documents None 1197315617339724591437 /docs/en/application-note/AN3538.pdf 460604 /docs/en/application-note/AN3538.pdf AN3538 documents N 2007-12-10 Enabling and Checking DDR ECC on PowerQUICC<sup>&#174;</sup> II /docs/en/application-note/AN3538.pdf /docs/en/application-note/AN3538.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 10, 2007 645036621402383989 Application Note Y N Enabling and Checking DDR ECC on PowerQUICC<sup>&#174;</sup> II 17 1 English The enhanced three-speed Ethernet controller (eTSEC) offered on many PowerQUICC&#8482; II Pro, PowerQUICC&#8482; III, and other devices, allows for flexible manipulation of incoming and outgoing Ethernet data. One such feature is the ability to receive and propagate padded, or &#8220;shimmed,&#8221; OSI layer 2 data to accommodate custom routing or direction of Ethernet data within a network. This application note describes what the shimming functionality does and the details of how to best utilize it. 1196114880779719950774 PSP 497.2 KB None None documents None 1196114880779719950774 /docs/en/application-note/AN3537.pdf 497175 /docs/en/application-note/AN3537.pdf AN3537 documents N 2016-10-31 Accommodating Layer 2 Padding (Shimming) with the Enhanced Three-Speed Ethernet Controller (eTSEC) /docs/en/application-note/AN3537.pdf /docs/en/application-note/AN3537.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 6, 2007 645036621402383989 Application Note N Accommodating Layer 2 Padding (Shimming) with the Enhanced Three-Speed Ethernet Controller (eTSEC) 18 0 English This application note explains how to program one of the eLBC&#8217;s user-programmable machines (UPMs) to control an SDRAM memory device. 1194558645992741221612 PSP 574.8 KB None None documents None 1194558645992741221612 /docs/en/application-note/AN3533.pdf 574761 /docs/en/application-note/AN3533.pdf AN3533 documents N 2007-11-08 Programming the User-Programmable Machine (UPM) for SDRAM Memory Devices /docs/en/application-note/AN3533.pdf /docs/en/application-note/AN3533.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 8, 2007 645036621402383989 Application Note Y N Programming the User-Programmable Machine (UPM) for SDRAM Memory Devices 19 2 English These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. 1128961595061725581551 PSP 619.7 KB None None documents None 1128961595061725581551 /docs/en/application-note/AN2910.pdf 619650 /docs/en/application-note/AN2910.pdf AN2910 documents N 2016-10-31 Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf /docs/en/application-note/AN2910.pdf Application Note N 645036621402383989 2022-12-07 pdf en Mar 27, 2007 645036621402383989 Application Note N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces Application Note Software Application Note Software 2 20 0 English 1258066894053701788655 PSP 330.9 KB Registration With Click-Thru Software Licensing Agreement 1395958162559706127527 documents Extended 1258066894053701788655 /secured/assets/documents/en/application-note-software/AN3966SW.zip 330857 /secured/assets/documents/en/application-note-software/AN3966SW.zip AN3966SW documents Y N 2016-10-31 Software to accompany application note AN3966 /webapp/Download?colCode=AN3966SW&appType=license /secured/assets/documents/en/application-note-software/AN3966SW.zip Application Note Software N 789425793691620447 2022-12-07 zip Y en Nov 10, 2009 789425793691620447 Application Note Software N Software to accompany application note AN3966 21 0 English 1197316910103728130595 PSP 193.9 KB None None documents None 1197316910103728130595 /docs/en/application-note-software/AN3538SW.zip 193903 /docs/en/application-note-software/AN3538SW.zip AN3538SW documents N 2007-12-10 Software Package for Enabling and Checking DDR ECC on PowerQUICC<sup>&#174;</sup>&#8482; II Pro /docs/en/application-note-software/AN3538SW.zip /docs/en/application-note-software/AN3538SW.zip Application Note Software N 789425793691620447 2022-12-07 zip en Dec 10, 2007 789425793691620447 Application Note Software D N Software Package for Enabling and Checking DDR ECC on PowerQUICC<sup>&#174;</sup>&#8482; II Pro Brochure Brochure 1 22 1 English NXP, known for its&#13;&#10;design and integration capabilities, designed&#13;&#10;the versatile MPC8313E, MPC8315E and&#13;&#10;MPC8314E PowerQUICC<sup>&#174;</sup>&#174; processors to&#13;&#10;integrate hardware for Ethernet and serial&#13;&#10;communications, memory interfaces, USB&#13;&#10;ports, security and other popular inputs&#13;&#10;and outputs in a ubiquitous architecture&#13;&#10;engineered to serve several markets equally&#13;&#10;well. 1208376113735717128975 PSP 828.2 KB None None documents None 1208376113735717128975 /docs/en/brochure/MPC831x_Brochure.pdf 828236 /docs/en/brochure/MPC831x_Brochure.pdf MPC831X_BROCHURE documents N 2008-04-16 MPC831x /docs/en/brochure/MPC831x_Brochure.pdf /docs/en/brochure/MPC831x_Brochure.pdf Brochure N 712453003803778552 2022-12-07 pdf en Apr 16, 2008 712453003803778552 Brochure Y N MPC831x Errata Errata 1 23 4 English This document details all known silicon errata for the MPC8315E, MPC8315, MPC8314E, and MPC8314. 1234987349321743268551 PSP 632.3 KB None None documents None 1234987349321743268551 /docs/en/errata/MPC8315ECE.pdf 632323 /docs/en/errata/MPC8315ECE.pdf MPC8315ECE documents N N 2009-02-18 MPC8315E Chip Errata - Chip Errata /docs/en/errata/MPC8315ECE.pdf /docs/en/errata/MPC8315ECE.pdf Errata N 155452329886410597 2022-12-07 pdf N en May 27, 2014 155452329886410597 Errata Y N MPC8315E Chip Errata - Chip Errata Fact Sheet Fact Sheet 2 24 2 English The MPC8315E-RDB reference platform is&#13;&#10;ideal for hardware and software development&#13;&#10;of the two-drive consumer network&#13;&#10;attached storage (NAS) and the digital&#13;&#10;media server. 1192385286095718074509 PSP 585.1 KB None None documents None 1192385286095718074509 /docs/en/fact-sheet/MPC8315ERDBFS.pdf 585146 /docs/en/fact-sheet/MPC8315ERDBFS.pdf MPC8315ERDBFS documents N N 2020-02-17 MPC8315E-RDB Reference Platform Fact Sheet /docs/en/fact-sheet/MPC8315ERDBFS.pdf /docs/en/fact-sheet/MPC8315ERDBFS.pdf Fact Sheet N 736675474163315314 2022-12-07 pdf N en Apr 6, 2009 736675474163315314 Fact Sheet Y N MPC8315E-RDB Reference Platform Fact Sheet 25 4 English QUICC Engine<sup>&#174;</sup>TM and Enhanced Triple Speed Ethernet Controller (eTSEC) are the first NXP communications interfaces to optimize IEEE 1588 Precision Time Protocol (PTP) in hardware. 1153163047046710587034 PSP 216.3 KB None None documents None 1153163047046710587034 /docs/en/fact-sheet/PQIEEE1588FS.pdf 216278 /docs/en/fact-sheet/PQIEEE1588FS.pdf PQIEEE1588FS documents N N 2016-10-31 PowerQUICC Integrates IEEE 1588 Time Synchronization /docs/en/fact-sheet/PQIEEE1588FS.pdf /docs/en/fact-sheet/PQIEEE1588FS.pdf Fact Sheet N 736675474163315314 2022-12-07 pdf N en Feb 14, 2008 736675474163315314 Fact Sheet Y N PowerQUICC Integrates IEEE 1588 Time Synchronization Supporting Information Supporting Information 2 26 1.9 English FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. 1368836090577704535160 PSP 303.5 KB None None documents None 1368836090577704535160 /docs/en/supporting-information/FSLNISTCAVP.pdf 303546 /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP documents N N 2016-11-09 FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf /docs/en/supporting-information/FSLNISTCAVP.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 28, 2016 371282830530968666 Supporting Information Y N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 27 2 English Customer Export Control Information Document 1232680180316716864168 PSP 236.6 KB None None documents None 1232680180316716864168 /docs/en/supporting-information/MPC8315EFAMPECI.pdf 236569 /docs/en/supporting-information/MPC8315EFAMPECI.pdf MPC8315EFAMPECI documents N N 2016-10-31 MPC8315E Family Customer Export Control Information /docs/en/supporting-information/MPC8315EFAMPECI.pdf /docs/en/supporting-information/MPC8315EFAMPECI.pdf Supporting Information N 371282830530968666 2023-06-19 pdf N en Dec 10, 2010 371282830530968666 Supporting Information Y N MPC8315E Family Customer Export Control Information White Paper White Paper 2 28 3 English Network security protocols and applications use a variety of cryptographic algorithms to achieve these high-level goals. Because cryptography is computationally intensive, hardware acceleration is highly desirable when cryptographic algorithms are frequent system functions. 1227561595497709456436 PSP 580.1 KB Registration without Disclaimer None documents Extended 1227561595497709456436 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf 580121 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf CRYPTOWP documents Y N 2016-10-31 Understanding Cryptographic Performance /webapp/Download?colCode=CRYPTOWP /secured/assets/documents/en/white-paper/CRYPTOWP.pdf White Paper N 918633085541740938 2022-12-07 pdf Y en Aug 15, 2008 918633085541740938 White Paper Y N Understanding Cryptographic Performance 29 0 English The focus of this white paper is to provide the end user with high level design considerations and/or trade-offs associated with migrating from SDRAM to DDR SDRAM-based designs. 1208376896761708228520 PSP 735.3 KB None None documents None 1208376896761708228520 /docs/en/white-paper/DDRSDRAMWP.pdf 735286 /docs/en/white-paper/DDRSDRAMWP.pdf DDRSDRAMWP documents N N 2016-10-31 Comparison of DDRx and SDRAM /docs/en/white-paper/DDRSDRAMWP.pdf /docs/en/white-paper/DDRSDRAMWP.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Apr 16, 2008 918633085541740938 White Paper Y N Comparison of DDRx and SDRAM false 0 MPC8315E downloads en true 1 Y PSP Application Note 14 /docs/en/application-note/AN13461.pdf 2022-01-04 1641302649210707506203 PSP 6 Nov 30, 2021 Application Note Reviewing the troubleshoot microcontroller when there is a malfunction module. None /docs/en/application-note/AN13461.pdf English documents 302971 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN13461.pdf AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note /docs/en/application-note/AN13461.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note 303.0 KB AN13461 N 1641302649210707506203 /secured/assets/documents/en/application-note/AN3645.pdf 2016-10-31 1224778148188710027580 PSP 7 Apr 28, 2017 Application Note This document is a supplement to the SEC 2/3x reference device driver. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3645.pdf English documents 1147132 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3645 SEC 2/3x Descriptor Programmer’s Guide /secured/assets/documents/en/application-note/AN3645.pdf documents 645036621402383989 Application Note N en Extended pdf 3 Y N SEC 2/3x Descriptor Programmer’s Guide 1.1 MB AN3645 N 1224778148188710027580 /docs/en/application-note/AN2583.pdf 2003-12-01 1070297961506735248621 PSP 8 Jul 29, 2014 Application Note AN2583: This application note provides programming guidelines for the PowerQUICC<sup>&#174;</sup> DDR-SDRAM memory controller and specifically JEDEC-compatible DDR1 SDRAM memories. None /docs/en/application-note/AN2583.pdf English documents 333170 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN2583.pdf AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note /docs/en/application-note/AN2583.pdf documents 645036621402383989 Application Note N en None Y pdf 11 N N AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note 333.2 KB AN2583 N 1070297961506735248621 /docs/en/application-note/AN3438.pdf 2009-04-14 1239732833133697944315 PSP 9 Feb 16, 2012 Application Note This application note describes the generally recommended connections for the new designs based on the NXP MPC8315E and MPC8315 processors. None /docs/en/application-note/AN3438.pdf English documents 325357 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3438.pdf Design Checklist for PowerQUICC<sup>&#174;</sup>&#8482; II Pro MPC8315E Processor /docs/en/application-note/AN3438.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N Design Checklist for PowerQUICC<sup>&#174;</sup>&#8482; II Pro MPC8315E Processor 325.4 KB AN3438 N 1239732833133697944315 /secured/assets/documents/en/application-note/AN4311.pdf 2016-10-31 1305312143395731535528 PSP 10 May 13, 2011 Application Note This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4311.pdf English documents 577164 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4311 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /secured/assets/documents/en/application-note/AN4311.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev. 0 Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 577.2 KB AN4311 N 1305312143395731535528 /docs/en/application-note/AN3830.pdf 2009-06-19 1245429781973738421244 PSP 11 Feb 1, 2011 Application Note AN3830: This application note provides a practical guide to using Our CodeWarrior IDE to debug hardware. Focusing on PowerQUICC<sup>&#174;</sup> processors, this document covers many of the key features available in the IDE to assist in bring-up and troubleshooting of a new board. None /docs/en/application-note/AN3830.pdf English documents 1576181 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3830.pdf AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes /docs/en/application-note/AN3830.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes 1.6 MB AN3830 N 1245429781973738421244 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 12 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939 DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 /docs/en/application-note/AN4026.pdf 2009-12-17 1260992898773711434436 PSP 13 Dec 17, 2009 Application Note A common use of the QUICC Engine block is to establish an HDLC communication path over a TDM interface, such as a T1 or E1 link. This application note describes the various sub-blocks used in the QUICC Engine communications engine for this application, discusses how the sub-blocks interoperate with each other, describes how to initialize them for the HDLC communication path, and provides a software demonstration of HDLC mode via a TDM interface using on-chip loopback. None /docs/en/application-note/AN4026.pdf English documents 718019 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4026.pdf Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC /docs/en/application-note/AN4026.pdf documents 645036621402383989 Application Note N en None pdf 0 N Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC 718.0 KB AN4026 N 1260992898773711434436 /docs/en/application-note/AN3966.pdf 2016-10-31 1258066893562722616236 PSP 14 Nov 10, 2009 Application Note High-level data link control (HDLC) is widely used in the telecommunications and networking industries. NXP&#8217;s PowerQUICC&#8482; communications processors have extensive support for HDLC protocol through the communications processor module (CPM) and QUICC Engine&#8482; technologies.&#13;&#10;&#13;&#10;This application note explains how NXP&#8217;s existing&#13;&#10;PowerQUICC communications processors use the CPM and QUICC Engine technologies to support the HDLC protocol and provides HDLC e None /docs/en/application-note/AN3966.pdf English documents 496625 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3966.pdf PowerQUICC™ HDLC Support and Example Code /docs/en/application-note/AN3966.pdf documents 645036621402383989 Application Note N en None pdf 0 N PowerQUICC™ HDLC Support and Example Code 496.6 KB AN3966 N 1258066893562722616236 /docs/en/application-note/AN3544.pdf 2016-10-31 1198270786976715604383 PSP 15 Dec 21, 2007 Application Note This application note provides an overview and specific strategies for cache coherency and potential performance impacts in the PowerQUICC<sup>&#174;</sup> II Pro and PowerQUICC III families. It focuses on data coherency and potential system issues, as well as some concerns associated with having multiple DMA devices. It also discusses the specific steps and interdependencies required to implement hardware enforced cache coherency. None /docs/en/application-note/AN3544.pdf English documents 547694 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3544.pdf PowerQUICC™ Data Cache Coherency /docs/en/application-note/AN3544.pdf documents 645036621402383989 Application Note N en None pdf 0 N PowerQUICC™ Data Cache Coherency 547.7 KB AN3544 N 1198270786976715604383 /docs/en/application-note/AN3538.pdf 2007-12-10 1197315617339724591437 PSP 16 Dec 10, 2007 Application Note This application note explains how to configure the memory controller to use ECC and how to use some of its test capabilities to validate correct ECC operation for the PowerQUICC<sup>&#174;</sup> II Pro family. None /docs/en/application-note/AN3538.pdf English documents 460604 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3538.pdf Enabling and Checking DDR ECC on PowerQUICC<sup>&#174;</sup> II /docs/en/application-note/AN3538.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N Enabling and Checking DDR ECC on PowerQUICC<sup>&#174;</sup> II 460.6 KB AN3538 N 1197315617339724591437 /docs/en/application-note/AN3537.pdf 2016-10-31 1196114880779719950774 PSP 17 Dec 6, 2007 Application Note The enhanced three-speed Ethernet controller (eTSEC) offered on many PowerQUICC&#8482; II Pro, PowerQUICC&#8482; III, and other devices, allows for flexible manipulation of incoming and outgoing Ethernet data. One such feature is the ability to receive and propagate padded, or &#8220;shimmed,&#8221; OSI layer 2 data to accommodate custom routing or direction of Ethernet data within a network. This application note describes what the shimming functionality does and the details of how to best utilize it. None /docs/en/application-note/AN3537.pdf English documents 497175 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3537.pdf Accommodating Layer 2 Padding (Shimming) with the Enhanced Three-Speed Ethernet Controller (eTSEC) /docs/en/application-note/AN3537.pdf documents 645036621402383989 Application Note N en None pdf 1 N Accommodating Layer 2 Padding (Shimming) with the Enhanced Three-Speed Ethernet Controller (eTSEC) 497.2 KB AN3537 N 1196114880779719950774 /docs/en/application-note/AN3533.pdf 2007-11-08 1194558645992741221612 PSP 18 Nov 8, 2007 Application Note This application note explains how to program one of the eLBC&#8217;s user-programmable machines (UPMs) to control an SDRAM memory device. None /docs/en/application-note/AN3533.pdf English documents 574761 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3533.pdf Programming the User-Programmable Machine (UPM) for SDRAM Memory Devices /docs/en/application-note/AN3533.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N Programming the User-Programmable Machine (UPM) for SDRAM Memory Devices 574.8 KB AN3533 N 1194558645992741221612 /docs/en/application-note/AN2910.pdf 2016-10-31 1128961595061725581551 PSP 19 Mar 27, 2007 Application Note These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. None /docs/en/application-note/AN2910.pdf English documents 619650 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2910.pdf Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf documents 645036621402383989 Application Note N en None pdf 2 N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces 619.7 KB AN2910 N 1128961595061725581551 Application Note Software 2 /secured/assets/documents/en/application-note-software/AN3966SW.zip 2016-10-31 1258066894053701788655 PSP 20 Nov 10, 2009 Application Note Software Registration With Click-Thru Software Licensing Agreement /secured/assets/documents/en/application-note-software/AN3966SW.zip English documents 330857 1395958162559706127527 789425793691620447 2022-12-07 Y /webapp/Download?colCode=AN3966SW&appType=license Software to accompany application note AN3966 /secured/assets/documents/en/application-note-software/AN3966SW.zip documents 789425793691620447 Application Note Software N en Extended zip 0 Y N Software to accompany application note AN3966 330.9 KB AN3966SW N 1258066894053701788655 /docs/en/application-note-software/AN3538SW.zip 2007-12-10 1197316910103728130595 PSP 21 Dec 10, 2007 Application Note Software None /docs/en/application-note-software/AN3538SW.zip English documents 193903 None 789425793691620447 2022-12-07 /docs/en/application-note-software/AN3538SW.zip Software Package for Enabling and Checking DDR ECC on PowerQUICC<sup>&#174;</sup>&#8482; II Pro /docs/en/application-note-software/AN3538SW.zip documents 789425793691620447 Application Note Software N en None D zip 0 N Software Package for Enabling and Checking DDR ECC on PowerQUICC<sup>&#174;</sup>&#8482; II Pro 193.9 KB AN3538SW N 1197316910103728130595 Brochure 1 /docs/en/brochure/MPC831x_Brochure.pdf 2008-04-16 1208376113735717128975 PSP 22 Apr 16, 2008 Brochure NXP, known for its&#13;&#10;design and integration capabilities, designed&#13;&#10;the versatile MPC8313E, MPC8315E and&#13;&#10;MPC8314E PowerQUICC<sup>&#174;</sup>&#174; processors to&#13;&#10;integrate hardware for Ethernet and serial&#13;&#10;communications, memory interfaces, USB&#13;&#10;ports, security and other popular inputs&#13;&#10;and outputs in a ubiquitous architecture&#13;&#10;engineered to serve several markets equally&#13;&#10;well. None /docs/en/brochure/MPC831x_Brochure.pdf English documents 828236 None 712453003803778552 2022-12-07 /docs/en/brochure/MPC831x_Brochure.pdf MPC831x /docs/en/brochure/MPC831x_Brochure.pdf documents 712453003803778552 Brochure N en None Y pdf 1 N MPC831x 828.2 KB MPC831X_BROCHURE N 1208376113735717128975 Data Sheet 1 /docs/en/data-sheet/MPC8315EEC.pdf 2009-05-10 1241818921035699995918 PSP 4 Nov 23, 2011 Data Sheet Data Sheet This document provides an overview of the MPC8315E PowerQUICC<sup>&#174;</sup>&#8482; II Pro processor features, including a block diagram showing the major functional components. None /docs/en/data-sheet/MPC8315EEC.pdf English 676915 None Data Sheet 2022-12-07 N /docs/en/data-sheet/MPC8315EEC.pdf MPC8315E PowerQUICC<sup>&#174;</sup> II Pro Processor Hardware Specifications /docs/en/data-sheet/MPC8315EEC.pdf documents 980000996212993340 Data Sheet N Y en None Y t520 pdf 2 N N MPC8315E PowerQUICC<sup>&#174;</sup> II Pro Processor Hardware Specifications 676.9 KB MPC8315EEC N 1241818921035699995918 Errata 1 /docs/en/errata/MPC8315ECE.pdf 2009-02-18 1234987349321743268551 PSP 23 May 27, 2014 Errata This document details all known silicon errata for the MPC8315E, MPC8315, MPC8314E, and MPC8314. None /docs/en/errata/MPC8315ECE.pdf English documents 632323 None 155452329886410597 2022-12-07 N /docs/en/errata/MPC8315ECE.pdf MPC8315E Chip Errata - Chip Errata /docs/en/errata/MPC8315ECE.pdf documents 155452329886410597 Errata N en None Y pdf 4 N N MPC8315E Chip Errata - Chip Errata 632.3 KB MPC8315ECE N 1234987349321743268551 Fact Sheet 3 /docs/en/fact-sheet/MPC8315ERDBFS.pdf 2020-02-17 1192385286095718074509 PSP 24 Apr 6, 2009 Fact Sheet The MPC8315E-RDB reference platform is&#13;&#10;ideal for hardware and software development&#13;&#10;of the two-drive consumer network&#13;&#10;attached storage (NAS) and the digital&#13;&#10;media server. None /docs/en/fact-sheet/MPC8315ERDBFS.pdf English documents 585146 None 736675474163315314 2022-12-07 N /docs/en/fact-sheet/MPC8315ERDBFS.pdf MPC8315E-RDB Reference Platform Fact Sheet /docs/en/fact-sheet/MPC8315ERDBFS.pdf documents 736675474163315314 Fact Sheet N en None Y pdf 2 N N MPC8315E-RDB Reference Platform Fact Sheet 585.1 KB MPC8315ERDBFS N 1192385286095718074509 /docs/en/fact-sheet/PQIEEE1588FS.pdf 2016-10-31 1153163047046710587034 PSP 25 Feb 14, 2008 Fact Sheet QUICC Engine<sup>&#174;</sup>TM and Enhanced Triple Speed Ethernet Controller (eTSEC) are the first NXP communications interfaces to optimize IEEE 1588 Precision Time Protocol (PTP) in hardware. None /docs/en/fact-sheet/PQIEEE1588FS.pdf English documents 216278 None 736675474163315314 2022-12-07 N /docs/en/fact-sheet/PQIEEE1588FS.pdf PowerQUICC Integrates IEEE 1588 Time Synchronization /docs/en/fact-sheet/PQIEEE1588FS.pdf documents 736675474163315314 Fact Sheet N en None Y pdf 4 N N PowerQUICC Integrates IEEE 1588 Time Synchronization 216.3 KB PQIEEE1588FS N 1153163047046710587034 /docs/en/fact-sheet/MPC8315EFS.pdf 2007-09-11 1189477170939723836600 PSP 1 Apr 1, 2009 Fact Sheet Fact Sheet The MPC8315E communications processor&#13;&#10;family enables a wide range of feature-rich&#13;&#10;applications that make the digital home&#13;&#10;experience easier, richer and safer. None /docs/en/fact-sheet/MPC8315EFS.pdf English 232152 None Fact Sheet 2022-12-07 /docs/en/fact-sheet/MPC8315EFS.pdf MPC8315E Fact Sheet /docs/en/fact-sheet/MPC8315EFS.pdf documents 736675474163315314 Fact Sheet N Y en None Y t523 pdf 3 N MPC8315E Fact Sheet 232.2 KB MPC8315EFS N 1189477170939723836600 Product Brief 1 /docs/en/product-brief/MPC8315EPB.pdf 2007-09-17 1190032659021723573365 PSP 3 Sep 14, 2007 Product Brief Product Brief This document provides an overview of the MPC8315E PowerQUICC<sup>&#174;</sup> II Pro processor features, including a block diagram showing the major functional components. None /docs/en/product-brief/MPC8315EPB.pdf English 519772 None Product Brief 2022-12-07 /docs/en/product-brief/MPC8315EPB.pdf MPC8315E Product Brief /docs/en/product-brief/MPC8315EPB.pdf documents 899114358132306053 Product Brief N Y en None Y t532 pdf 0 N MPC8315E Product Brief 519.8 KB MPC8315EPB N 1190032659021723573365 Reference Manual 2 /docs/en/reference-manual/MPC8315ERMAD.pdf 2008-04-04 1207167761981697706467 PSP 5 Sep 20, 2010 Reference Manual This errata describes corrections to the MPC8315E PowerQUICC<sup>&#174;</sup>&#8482; II Pro Integrated Host Processor&#13;&#10;Family Reference Manual, Revision 2. None /docs/en/reference-manual/MPC8315ERMAD.pdf English documents 509070 None 500633505221135046 2022-12-07 /docs/en/reference-manual/MPC8315ERMAD.pdf Errata to MPC8315E PowerQUICC<sup>&#174;</sup>&#8482; II Pro Integrated Host Processor Family Reference Manual, Rev. 1 /docs/en/reference-manual/MPC8315ERMAD.pdf documents 500633505221135046 Reference Manual N en None Y pdf 2.1 N Errata to MPC8315E PowerQUICC<sup>&#174;</sup>&#8482; II Pro Integrated Host Processor Family Reference Manual, Rev. 1 509.1 KB MPC8315ERMAD N 1207167761981697706467 /docs/en/reference-manual/MPC8315ERM.pdf 2007-09-12 1189648881727718440864 PSP 2 Jun 29, 2010 Reference Manual Reference Manual This reference manual defines the functionality of the MPC8315E. It is written from the perspective of the MPC8315E, which is the superset device, and unless otherwise noted, the information applies also to the MPC8315, MPC8314E, and MPC8314. Note that the MPC8315 and MPC8314 do not support a security engine. Also, the MPC8314E and MPC8314 do not support dual SATA controllers. None /docs/en/reference-manual/MPC8315ERM.pdf English 12834772 None Reference Manual 2022-12-07 /docs/en/reference-manual/MPC8315ERM.pdf MPC8315E Reference Manual /docs/en/reference-manual/MPC8315ERM.pdf documents 500633505221135046 Reference Manual N Y en None Y t877 pdf 2 N MPC8315E Reference Manual 12.8 MB MPC8315ERM N 1189648881727718440864 Supporting Information 2 /docs/en/supporting-information/FSLNISTCAVP.pdf 2016-11-09 1368836090577704535160 PSP 26 Oct 28, 2016 Supporting Information FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. None /docs/en/supporting-information/FSLNISTCAVP.pdf English documents 303546 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1.9 N N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 303.5 KB FSLNISTCAVP N 1368836090577704535160 /docs/en/supporting-information/MPC8315EFAMPECI.pdf 2016-10-31 1232680180316716864168 PSP 27 Dec 10, 2010 Supporting Information Customer Export Control Information Document None /docs/en/supporting-information/MPC8315EFAMPECI.pdf English documents 236569 None 371282830530968666 2023-06-19 N /docs/en/supporting-information/MPC8315EFAMPECI.pdf MPC8315E Family Customer Export Control Information /docs/en/supporting-information/MPC8315EFAMPECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 2 N N MPC8315E Family Customer Export Control Information 236.6 KB MPC8315EFAMPECI N 1232680180316716864168 White Paper 2 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf 2016-10-31 1227561595497709456436 PSP 28 Aug 15, 2008 White Paper Network security protocols and applications use a variety of cryptographic algorithms to achieve these high-level goals. Because cryptography is computationally intensive, hardware acceleration is highly desirable when cryptographic algorithms are frequent system functions. Registration without Disclaimer /secured/assets/documents/en/white-paper/CRYPTOWP.pdf English documents 580121 None 918633085541740938 2022-12-07 Y /webapp/Download?colCode=CRYPTOWP Understanding Cryptographic Performance /secured/assets/documents/en/white-paper/CRYPTOWP.pdf documents 918633085541740938 White Paper N en Extended Y pdf 3 Y N Understanding Cryptographic Performance 580.1 KB CRYPTOWP N 1227561595497709456436 /docs/en/white-paper/DDRSDRAMWP.pdf 2016-10-31 1208376896761708228520 PSP 29 Apr 16, 2008 White Paper The focus of this white paper is to provide the end user with high level design considerations and/or trade-offs associated with migrating from SDRAM to DDR SDRAM-based designs. None /docs/en/white-paper/DDRSDRAMWP.pdf English documents 735286 None 918633085541740938 2023-06-19 N /docs/en/white-paper/DDRSDRAMWP.pdf Comparison of DDRx and SDRAM /docs/en/white-paper/DDRSDRAMWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N N Comparison of DDRx and SDRAM 735.3 KB DDRSDRAMWP N 1208376896761708228520 true Y Products

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