Low-Power PowerQUICC® II Pro Processor with DDR2, eSDHC, 128-ch. HDLC/TDM, 10/100 Ethernet, USB, IEEE® 1588 | NXP Semiconductors

Low-Power PowerQUICC® II Pro Processor with DDR2, eSDHC, 128-ch. HDLC/TDM, 10/100 Ethernet, USB, IEEE® 1588

Block Diagram

NXP PowerQUIICC MPC8309 Communications Processor Block Diagram

NXP<sup>&#174;</sup> PowerQUIICC MPC8309 Communications Processor Block Diagram

Features

  • e300 core running up to 417 MHz, DDR2 @ 266 MHz
  • QUICC Engine® running up to 200 MHz
  • 2 x HDLC/TDM
  • 3 x 10/100 or 2 x 10/100 w/IEEE1588v2
  • USB 2.0
  • eSDHC (boot from eSDHC support)
  • 4 x CAN
  • 4 x UART
  • 32-bit PCI Interface
  • Local bus (boot from NOR/NAND flash memory support)
  • 1.03W typical at 333 MHz e300 core/200 MHz QUICC Engine (maximum = 1.37W)
  • 489-pin, 19 mm x 19 mm MAPBGA package
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years.

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Documentation

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Compact List

Application Note (7)
Data Sheet (1)
Errata (1)
Fact Sheet (1)
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Design Files

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1 design file

Hardware

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4 hardware offerings

Software

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Note: For better experience, software downloads are recommended on desktop.

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