LPC43S20FET180|Arm Cortex-M4/M0|32-bit MCU

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The LPC43S20FET180 is a Arm Cortex-M4 based microcontroller for embedded applications which includes an Arm Cortex-M0 coprocessor, 200 kB of SRAM, security features with AES engine, advanced configurable peripherals such as the State Configurable Timer/PWM (SCTimer/PWM) and the Serial General-Purpose I/O (SGPIO) interface, High-speed USB controller, an external memory controller, and multiple digital and analog peripherals. The LPC43S20FET180 operates at CPU frequencies of up to 204 MHz.

The Arm Cortex-M4 is a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The Arm Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The Arm Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point unit is integrated in the core.

The Arm Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor offers up to 204 MHz performance with a simple instruction set and reduced code size. In LPC43Sx0, the Cortex-M0 coprocessor hardware multiply is implemented as a 32-cycle iterative multiplier.

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Data Sheet

Application Notes

Product Details

Features

Cortex-M4 Processor core
- Arm Cortex-M4 processor, running at frequencies of up to 204 MHz.
- Built-in Memory Protection Unit (MPU) supporting eight regions.
- Built-in Nested Vectored Interrupt Controller (NVIC).
- Hardware floating-point unit making the core a Cortex-M4.
- Non-maskable Interrupt (NMI) input.
- JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch points.
- Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
- System tick timer.
Cortex-M0 Processor core
- Arm Cortex-M0 coprocessor capable of off-loading the main Arm Cortex-M4F application processor.
- Running at frequencies of up to 204 MHz.
- JTAG
- Built-in NVIC.
On-chip memory
- 200 kB SRAM for code and data use.
- Multiple SRAM blocks with separate bus access. Two SRAM blocks can be powered down individually
- 64 kB ROM containing boot code and on-chip software drivers.
- 64 bit general-purpose OTP memory
- Two banks (256 bit total) One-Time Programmable (OTP) memory for AES key storage One bank can store an encrypted key for decoding the boot image.
AES engine for encryption and decryption of the boot image and data with DMA support and programmable via a ROM-based API.
Clock generation unit
- Crystal oscillator with an operating range of 1 MHz to 25 MHz.
- 12 MHz Internal RC (IRC) oscillator trimmed to 1.5 % accuracy over temperature and voltage.
- Ultra-low power Real-Time Clock (RTC) crystal oscillator.
- Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the third PLL can be used as audio PLL.
- Clock output.
Configurable digital peripherals
- Serial GPIO (SGPIO) interface.
- State Configurable Timer (SCTimer/PWM) subsystem on AHB.
- Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like the timers, SCTimer/PWM, and ADC0/1.
Serial interfaces
- Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 52 MB per second.
- One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY (USB0).
- USB interface electrical test software included in ROM USB stack.
- Four 550 UARTs with DMA support: one UART with full modem interface; one UART with IrDA interface; three USARTs support UART synchronous mode and a smart card interface conforming to ISO7816 specification.
- Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller excludes operation of all other peripherals connected to the same bus bridge
- Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support.
- One SPI controller.
- One Fast-mode Plus I²C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I²C-bus specification. Supports data rates of up to 1 Mbit/s.
- One standard I²C-bus interface with monitor mode and with standard I/O pins.
- Two I²S interfaces, each with DMA support and with one input and one output.
Digital peripherals
- External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices.
- Secure Digital Input Output (SD/MMC) card interface.
- Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB followers
- Up to 118 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors.
- GPIO registers are located on the AHB for fast access. GPIO ports have DMA support.
- Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources.
- Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.
- Four general-purpose timer/counters with capture and match capabilities.
- One motor control Pulse Width Modulator (PWM) for three-phase motor control.
- Repetitive Interrupt timer (RI timer).
- Windowed watchdog timer (WWDT).
- Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers.
- Alarm timer; can be battery powered.
Analog peripherals
- One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
- Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s. Up to eight input channels per ADC.
Unique ID for each device.
Power
- Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for the core supply and the RTC power domain.
- RTC power domain can be powered separately by a 3 V battery supply.
- Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
- Processor wake-up from Sleep mode via wake-up interrupts from various peripherals.
- Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain.
- Brownout detect with four separate thresholds for interrupt and forced reset.
- Power-On Reset (POR).
- Available as TFBGA100 package.

Target Applications

Communication hubs
Automotive aftermarket
Power management
Consumer health devices
Embedded audio applications
Industrial control
Industrial automation
White goods

Buy/Parametrics

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Documentation

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1-5 of 12 documents

Data Sheet
32-bit Arm^® Cortex^®-M4/M0 flashless MCU with security features; up to 264 kB SRAM, Ethernet; two HS USBs, AES engine, LCD, EMC, SPIFI

PDFRev 1.3Feb 5, 20207.3 MBLPC43S50_30_20English
Application Note
USBD Library for LPC4300/LPC1800 series MCUs

ZIPRev 1.0Jul 9, 20188.6 MBTN00041English
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Connecting TFT LCD with LCD controller of LPC MCU

ZIPRev 1Aug 22, 20173.2 MBAN12027English
Application Note
LPC18S/43S00, LPC18/4300 Random Number Generator

ZIPRev 1.0Aug 8, 2016101.4 MBAN11643English
Application Note
LPC18Sxx/43Sxx Secure Boot from QSPI Device

ZIPRev 1.1Feb 26, 20151.0 MBAN11648English
Application Note
LPC18Sxx/43Sxx Hardware Versus Software AES Benchmark

ZIPRev 1.0Feb 23, 20159.9 MBAN11649English
User Guide
LPC43xx/LPC43Sxx Arm® Cortex®-M4/M0 multi-core microcontroller

PDFRev 2.5Sep 13, 201913.6 MBUM10503English

Account Required
User Guide
LPC18xx Arm^® Cortex^®-M3 microcontroller

PDFRev 3.1Sep 13, 201911.9 MBUM10430English

Account Required
Errata
Errata sheet LPC43S50, LPC43S30, LPC43S20

PDFRev 1.8Feb 5, 20201.3 MBES_LPC43SX0English
Fact Sheet
LPC43Sxx Series of MCUs - Fact Sheet

PDFRev 1.0Jul 27, 2016952.0 KBLPC43SXXLFEnglish
Package Information
thin fine-pitch ball grid array package; 180 balls

PDFRev 1.0Feb 8, 2016536.0 MBSOT570-3English
Training Presentation
Driving LPC1700/LPC1800/LPC4300 with EPSON Crystals

PDFRev 1.1Nov 27, 2015213.7 KBR_10076English

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2 design files

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Models
BSDL for LPC18xx and LPC43xx

ZIPRev 2Feb 27, 2018 11:57:00269.0 KBBSDL_LPC18XX_43XX

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Symbols and Footprints
LPC43xx/LPC18xx Eagle symbols

ZIPRev 0Jun 3, 2016 00:00:0014.9 KBLPC43XX-EAGLE-SYM

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