S12ZVL Mixed-Signal MCU|MagniV

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S12 MagniV Mixed-Signal MCUs
S12ZVL Mixed-Signal MCU for Automotive and Industrial LIN Applications

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The S12ZVL platform, part of the S12 MagniV mixed-signal MCU product line, offers a low-cost, highly integrated solution for space-constrained automotive LIN nodes. With memory sizes from 8-128K flash, the family provides scalability for platform standardization.

The S12ZVL integrates a sophisticated S12Z core with a 12 V to 5 V voltage regulator and a LIN physical layer transceiver for automotive and industrial applications such as sensor interfaces, actuators, switch panels or ambient lighting.

Reference Manual

Application Notes

Product Details

Block Diagram

S12 MagniV Mixed-Signal MCU for LIN Applications Block Diagram

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Features

S12Z core - 32 MHz bus speed
Up to 128 KB Flash (with ECC)
High temperature (up to 150^º C ambient)
Up to 2KB EEPROM (with ECC)
Up to 8 KB RAM (with ECC)
Analog comparator and DAC
PGA
12V Vreg to supply device + ext comp- 70mA total (170mA with ext. Ballast)
LIN physical layer
On-chip RC-oscillator trimmed to 1.3% accuracy, no ext xtal required on LIN

SafeAssure Program

Safe Assure^® (Functional Safety)

When it comes to functional safety, NXP stands for quality and reliability. Our SafeAssure program simplifies system-level safety requirements in accordance with ISO 26262.

S12ZVL Family Comparison

		48-LQFP
		S12ZVLA			S12ZVL			S12ZVL
Memory	Flash [kB]	128	96	64	128	96	64	32	16	8
	EEPROM [kB]	2		1	2		1	0.128
	RAM [kB]	8		4	8		4	1		0.5
UHV	V reg	5V / 3.3V ; 70mA or up to 170 (with ballast option / BCTL)						5V; 70mA or up to 170 (with ballast option / BCTL)
	V reg tolerance	2%			3%			3%
	PHY	LIN
	HVI	1
Analog	ADC (LB) channel	10
	ADC (LB) resolution	12 Bit			10 Bit			10 Bit
	ACMP with 8bit DAC	1			-			-
	PGA	1			-			-
	PGA levels	10/20/40/80x			-			-
Comms	SCI	2
	SPI	1
	IIC	1
	MSCAN	1						-
Tim	Timer (6+2ch)	6ch + 2ch (16 Bit)
PWM		8ch 8Bit (or 4ch 16Bit)
I/O	GPIO	35						-
	intrr. Cap. IO (5/12v)	22/1
	eVdd (5V/20mA)	1
	N-GPIOs (5V / 25mA)	3						1
	Temperature options	C / V / M						C / V / M

		32-LQFP						32-QFN			32-LQFP			32-QFN
		S12ZVLA			S12ZVL			S12ZVLA			S12ZVL			S12ZVLS
Memory	Flash [kB]	128	96	64	128	96	64	128	96	64	32	16	8	32	16
	EEPROM [kB]	2		1	2		1	2		1	0.128
	RAM [kB]	8		4	8		4	8		4	1		0.5	1
UHV	V reg	5V / 3.3V ; 70mA or up to 170 (with ballast option / BCTL)									5V; 70mA or up to 170 (with ballast option / BCTL)
	V reg tolerance	2%			3%			2%			3%
	PHY	LIN
	HVI	1
Analog	ADC (LB) channel	6						7			6
	ADC (LB) resolution	12 Bit			10 Bit			12 Bit			10 Bit
	ACMP with 8bit DAC	1			0			1			-
	PGA	1			-			1			-
	PGA levels	10/20/40/80x			-			10/20/40/80x			-
Comms	SCI	2
	SPI	1
	IIC	1
	MSCAN	1									-
Tim	Timer (6+2ch on silicon)	6ch + 2ch (16 Bit)
PWM		8ch (16Bit)									8ch 8Bit (or 4ch 16Bit)
I/O	GPIO	20
	intrr. Cap. IO (5/12v)	16/1
	eVdd (5V/20mA)	1
	N-GPIOs (5V / 25mA)	1									1			3
	Temperature options	C / V / M									C / V / M

Buy/Parametrics

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Design Resources

Design Files

Quick reference to our design files types.

4 design files

Receive the full breakdown. See the product footprint and more in the eCad file.

Symbols and Footprints
S12ZVL_48LQFP - CAD Symbol and PCB Footprint - BXL File

ZIPRev 0Sep 25, 2019 16:04:0034.5 KBS12ZVL_48LQFP-BXL
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Symbols and Footprints
S12ZVL_32QFN_EP - CAD Symbol and PCB Footprint - BXL File

ZIPRev 0Jun 27, 2019 14:44:0093.1 KBS9S12ZVLS16F0CFM
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Symbols and Footprints
S12ZVL_48LQFP - CAD Symbol and PCB Footprint - BXL File

ZIPRev 0Jun 27, 2019 14:44:0097.6 KBPC912ZVL32F0VLF
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Symbols and Footprints
S12ZVL_64LQFP_EP - CAD Symbol and PCB Footprint - BXL File

ZIPRev 0Jul 3, 2019 14:44:00121.6 KBS912ZVML12F1MKH
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