PCA9512ADP Product Information|NXP

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PCA9512ADP,118

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12NC: 935279719118

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Quantity

Unit Pricing

1 - 24$1.31
25 - 25$1.31
26 - 99$1.31
100+$1.31

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$1.31 USD
In Stock:2,440
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Operating Features

ParameterValue
Operating Temperature (°C)
-40~85
I2C-bus (kHz)
400
Operating voltage (VDC)
2.7~5.5
ParameterValue
Operating Voltage (V)
2.7~5.5
Inputs
1
Outputs
1

Environmental

Part/12NCPbFreeEU RoHSHalogen FreeRHF IndicatorREACH SVHCWeight (mg)
PCA9512ADP,118(935279719118)
Yes
Yes
Certificate Of Analysis (CoA)
Yes
DREACH SVHC
24.0

Quality

Part/12NCSafe Assure Functional SafetyMoisture Sensitivity Level (MSL)Peak Package Body Temperature (PPT) (C°)FITMTBFIR
Lead SolderingLead Free SolderingLead SolderingLead Free Soldering
PCA9512ADP,118
(935279719118)
No
1
1
240
260
2.0
5.0E8
0.0

Shipping

Part/12NCHarmonized Tariff (US)Disclaimer
PCA9512ADP,118
(935279719118)
854239

More about PCA9512A_PCA9512B

The PCA9512A/B is a hot swappable I²C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corruption of the data and clock buses and includes two dedicated supply voltage pins to provide level shifting between 3.3 V and 5 V systems while maintaining a better noise margin for each voltage level. Either pin may be powered with supply voltages ranging from 2.7 V to 5.5 V with no constraints on which supply voltage is higher. Control circuitry prevents the backplane from being connected to the card until a stop bit or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9512A/B provides bidirectional buffering, keeping the backplane and card capacitances isolated.

Both the PCA9512A and PCA9512B use identical silicon (PCN201012007F dated 13 Dec 2010), so the PCA9512B will be discontinued in the near future and is not recommended for new designs.

The PCA9512A/B rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements. The PCA9512A/B incorporates a digital input pin that enables and disables the rise time accelerators on all four SDAn and SCLn pins.

During insertion, the PCA9512A/B SDAn and SCLn pins are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip.

The incremental offset design of the PCA9510A/11A/12A/12B/13A/14A I/O drivers allows them to be connected to another PCA9510A/11A/12A/12B/13A/14A device in series or in parallel and to the I²C compliant side of static offset bus buffers, but not to the static offset side of those bus buffers.

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