Contactless Reader Module
NXP’s NFC readers are the active components in NFC transactions. They can read and write cards and tags, interact with NFC phones and enable communication from device to device. NXP has a broad portfolio of high-performance NFC readers, fully supporting the MIFARE® ICs and standards such as EMV, NFC readers portfolio is part of the EdgeVerse edge computing platform built on a foundation of scalability, energy efficiency, security, machine learning and connectivity.
Product Details
Supported Devices
Security and Authentication
Authentication
- SE051: EdgeLock® SE051: Proven, Easy-to-Use IoT Security Solution with Support for Updatability and Custom Applets
Processors and Microcontrollers
KM Series Arm Cortex-M0+
- TWO-PHASE-POWER-METER: Two-Phase Power Meter Reference Design
- KM3x: 50–75 MHz Precision Metrology MCUs with Segment LCDs Based on Arm® Cortex®-M0+
Analog and Mixed Signal
Real-Time Clocks
- PCF85363A: Tiny Real-Time Clock/Calendar with 64 B RAM, Alarm Function, Battery Switch-Over Time Stamp Input and I²C-Bus
Power Management
AC-DC Controllers with Integrated Power Switch
- TEA1723AT: HV Start-up Flyback Controller with Integrated MOSFET for 11 W Applications, F~Burst = 430 Hz
RFID
MIFARE DESFire
- MF3DHx3: MIFARE® DESFire® EV3: High-Security IC for Contactless Smart City Services
MIFARE Plus
- MFPEV2: MIFARE Plus® EV2: Secure IC for Contactless Smart City Services
NFC Readers
- CLRC66303HN: CLRC663 plus Family: High-Performance NFC Frontends
Features
MCU Features
- High-performance Arm® Cortex®-M0 core, up to 75 MHz of core clock frequency
- 512 KB/256 KB/64 KB single array flash
- Supports v6-M Instruction Set Architecture (ISA) including all 16-bit v7-M instructions plus a number of 32-bit thumb-2 instructions
- PLL to generate clocks for AFE
- FLL to generate core, system and flash clocks
- Flexible modes of operation
- Two internal trim-able clock references
Security
- Tamper detection with time stamping
- Random number generator, memory protection unit
- Memory Mapped Cryptographic Acceleration Unit (MMCAU) for AES Encryption
- Cyclic Redundancy Check (CRC)
CLRC66303 Multiple interfaces to support a broad range of microcontrollers
- Host interfaces: SPI, I²C, UART
- Up to 8 GPOs
- 512 byte FIFO buffer
- high-security reader using SAM interface
- Supported by NFC Cockpit and NFC Reader Library
- Complete range of development kits and boards
Documentation
Quick reference to our documentation types.
14 documents
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Data Sheet
Plug & Trust Secure Element
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Data Sheet
Kinetis KM35 Sub-Family Data Sheet
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Data Sheet
MIFARE Plus EV2
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Data Sheet
High performance NFC frontend CLRC661 plus
