Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
Package
TSSOP8: plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body
Buy Options
PCA9517ADP,118
Active
12NC: 935285764118
Details
Quantity
Unit Pricing
| 1 - 24 | $0.53 |
| 25 - 25 | $0.53 |
| 26 - 99 | $0.53 |
| 100+ | $0.53 |
Order
In Stock:340
Order from distributorsPCA9517ADP/DG,118
No Longer Manufactured
12NC: 935286938118
Details
Order
Operating Features
| Parameter | Value |
|---|---|
fi(RF) [max] (MHz) | 0.4 |
Number of pins | 8 |
Package Style | TSSOP |
Type Of Offset | Static Offset |
Inputs | 1 |
I2C-bus (kHz) | 400 |
Function | Static Offset |
Outputs | 1 |
Frequency (Min-Max) (MHz) | 0.4 |
Frequency Band (Hz) | 400000 |
Automotive | N |
Description | Dual Supply Level translating I2C-bus repeater |
VCC(B) (Min-Max) | 2.7 to 5.5 |
Operating Temperature (°C) | -40~85 |
VCC(A) (Min - Max) | 0.9 to 5.5 |
Supply Voltage [Min - Max] | 0.9, 2.7, 5.5, 5.5 |
Additional Features - Security | Static Offset |
AEC-Q100 compliant | N |
Frequency (Max) (MHz) | 0.4 |
| Parameter | Value |
|---|---|
AEC-Q100 compliant | N |
frange [max] (MHz) | 0.4 |
Type VLT | I2C Buffer with two Supplies |
Operating Voltage [Min to Max] (V) | 0.9 to 5.5, 2.7 to 5.5 |
Outputs | 1 |
Inputs | 1 |
Supply Voltage [max] (V) | 5.5 |
Ambient Operating Temperature (Min to Max) (℃) | -40 to 85 |
Supply Voltage [min] (V) | 0.9, 2.7 |
Tamb [min] (°C) | -40~85 |
Automotive Qualified | N |
Tamb (°C) | -40~85 |
Pad supply (V) | 0.9 to 5.5, 2.7 to 5.5 |
Supply Voltage [Min to Max] (V) | 0.9 to 5.5, 2.7 to 5.5 |
Number of Channels | 2 |
Operating Temperature (Min-Max) (℃) | -40 to 85 |
Operating Voltage (V) | 0.9~5.5 |
Operating Temperature (°C) | -40~85 |
Operating voltage (VDC) | 2.7~3.6_tolerant_to_5.5 VDC |
Environmental
| Part/12NC | PbFree | EU RoHS | Halogen Free | RHF Indicator | REACH SVHC | Weight (mg) |
|---|---|---|---|---|---|---|
PCA9517ADP,118(935285764118) | Yes | Yes Certificate Of Analysis (CoA) | Yes |  | REACH SVHC | 29.0054 |
PCA9517ADP/DG,118(935286938118) | Yes | Yes | Yes | | REACH SVHC | 22.1 |
Quality
| Part/12NC | Safe Assure Functional Safety | Moisture Sensitivity Level (MSL) | Peak Package Body Temperature (PPT) (C°) | FIT | MTBF | IR | ||
|---|---|---|---|---|---|---|---|---|
| Lead Soldering | Lead Free Soldering | Lead Soldering | Lead Free Soldering | |||||
PCA9517ADP,118 (935285764118) | No | 1 | 1 | 240 | 260 | 2.0 | 5.0E8 | 0.0 |
PCA9517ADP/DG,118 (935286938118) | No | 1 | 1 | 240 | 260 | 2.0 | 5.0E8 | 0.0 |
Shipping
| Part/12NC | Harmonized Tariff (US)Disclaimer |
|---|---|
PCA9517ADP,118 (935285764118) | 854239 |
PCA9517ADP/DG,118 (935286938118) | 854239 |
Discontinued and Replacement Part Data
| Part/12NC | Discontinuance Notice | Last Time Buy Date | Last Time Delivery Date | Replacement |
|---|---|---|---|---|
PCA9517ADP/DG,118 (935286938118) | - | 2009-03-31 | 2009-12-31 | PCA9517ADP,118 (935285764118) |
More about PCA9517A
The PCA9517A is a CMOS integrated circuit that provides level shifting between low voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I²C-bus or SMBus applications. While retaining all the operating modes and features of the I²C-bus system during the level shifts, it also permits extension of the I²C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Using the PCA9517A enables the system designer to isolate two halves of a bus for both voltage and capacitance. The SDA and SCL pins are overvoltage tolerant and are high-impedance when the PCA9517A is unpowered.
The 2.7 V to 5.5 V bus port B drivers behave much like the drivers on the PCA9515A device, while the adjustable voltage bus port A drivers drive more current and eliminate the static offset voltage. This results in a LOW on the port B translating into a nearly 0 V LOW on the port A which accommodates smaller voltage swings of lower voltage logic.
The static offset design of the port B PCA9517A I/O drivers prevent them from being connected to another device that has rise time accelerator including the PCA9510, PCA9511, PCA9512, PCA9513, PCA9514, PCA9515A, PCA9516A, PCA9517A (port B), or PCA9518. Port A of two or more PCA9517As can be connected together, however, to allow a star topography with port A on the common bus, and port A can be connected directly to any other buffer with static or dynamic offset voltage. Multiple PCA9517As can be connected in series, port A to port B, with no build-up in offset voltage with only time of flight delays to consider.
The PCA9517A drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above 2.5 V. The EN pin can also be used to turn the drivers on and off under system control. Caution should be observed to only change the state of the enable pin when the bus is idle.
The output pull-down on the port B internal buffer LOW is set for approximately 0.5 V, while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a lock-up condition from occurring. The output pull-down on port A drives a hard LOW and the input level is set at 0.3VCC(A) to accommodate the need for a lower LOW level in systems where the low voltage side supply voltage is as low as 0.9 V.
|
Parameter |
PCA9517[1] |
PCA9517A[2] |
|---|---|---|
|
electrostatic discharge, HBM |
> 2 kV |
> 5.5 kV |
[1] PCA9517 will be discontinued in several years, so move to the PCA9517A for all new designs and system updates.
[2] The PCA9517A is an improved hot swap and ESD version of the PCA9517, but otherwise operates identically and should be used for all new designs and system updates.