Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
Package
TSSOP8: plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body
Buy Options
PCA9510ADP,118
Active
12NC: 935279844118
Details
Quantity
Unit Pricing
| 1 - 24 | $1.47 |
| 25 - 25 | $1.47 |
| 26 - 99 | $1.47 |
| 100+ | $1.47 |
Order
In Stock:2,490
Order from distributorsOperating Features
| Parameter | Value |
|---|---|
Operating Temperature (°C) | -40~85 |
I2C-bus (kHz) | 400 |
Operating voltage (VDC) | 2.7~5.5 |
| Parameter | Value |
|---|---|
Inputs | 1 |
Outputs | 1 |
Environmental
| Part/12NC | PbFree | EU RoHS | Halogen Free | RHF Indicator | REACH SVHC | Weight (mg) |
|---|---|---|---|---|---|---|
PCA9510ADP,118(935279844118) | Yes | Yes Certificate Of Analysis (CoA) | Yes |  | REACH SVHC | 24.0 |
Quality
| Part/12NC | Safe Assure Functional Safety | Moisture Sensitivity Level (MSL) | Peak Package Body Temperature (PPT) (C°) | FIT | MTBF | IR | ||
|---|---|---|---|---|---|---|---|---|
| Lead Soldering | Lead Free Soldering | Lead Soldering | Lead Free Soldering | |||||
PCA9510ADP,118 (935279844118) | No | 1 | 1 | 240 | 260 | 2.0 | 5.0E8 | 0.0 |
Shipping
| Part/12NC | Harmonized Tariff (US)Disclaimer |
|---|---|
PCA9510ADP,118 (935279844118) | 854239 |
More about PCA9510A
The PCA9510A is a hot swappable I²C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9510A provides bidirectional buffering, keeping the backplane and card capacitances isolated.
The PCA9510A has no rise time accelerator circuitry to prevent interference when there are multiple devices in the same system. The PCA9510A incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a Low current mode when asserted LOW, and an open-drain READY output pin, which indicates that the backplane and card sides are connected together (HIGH) or not (LOW).
During insertion, the PCA9510A SDAIN and SCLIN pins (inputs only) are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip.
Remark: The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow them to be connected to another PCA9510A/11A/12A/13A/14A device in series or in parallel and to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A cannotconnect to the static offset I/Os used on the PCA9515/15A/16/16A/18 or PCA9517 B side or P82B96 Sx/y side.