Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
Package
LQFP48: LQFP48, plastic, low profile quad flat package; 48 terminals; 0.5 mm pitch; 7 mm x 7 mm x 1.4 mm body
Buy Options
DSP56F801FA80E
NRND
12NC: 935316525557
Details
Order
Operating Features
| Parameter | Value |
|---|---|
Flash (kB) | 16 |
RAM (kB) | 2 |
Operating Frequency [Max] (MHz) | 80 |
| Parameter | Value |
|---|---|
SPI | 1 |
Supply Voltage [Min to Max] (V) | 3 to 3.6 |
Environmental
| Part/12NC | PbFree | EU RoHS | Halogen Free | RHF Indicator | 2nd Level Interconnect | REACH SVHC | Weight (mg) |
|---|---|---|---|---|---|---|---|
DSP56F801FA80E(935316525557) | Yes | Yes Certificate Of Analysis (CoA) | Yes |  | e3 | REACH SVHC | 178.25 |
Quality
| Part/12NC | Safe Assure Functional Safety | Moisture Sensitivity Level (MSL) | Peak Package Body Temperature (PPT) (C°) | Maximum Time at Peak Temperatures (s) | |||
|---|---|---|---|---|---|---|---|
| Lead Free Soldering | Lead Free Soldering | Lead Free Soldering | |||||
DSP56F801FA80E (935316525557) | No | 3 | 260 | 40 | |||
Shipping
| Part/12NC | Harmonized Tariff (US)Disclaimer | Export Control Classification Number (US) |
|---|---|---|
DSP56F801FA80E (935316525557) | 854231 | 3A991A2 |
Product Change Notice
| Part/12NC | Issue Date | Effective Date | PCN | Title |
|---|---|---|---|---|
DSP56F801FA80E (935316525557) | 2025-04-16 | 2025-05-26 | 202504006I | Freescale Logo to NXP Logo Product Marking Conversion for All Remaining Former Freescale Products |
DSP56F801FA80E (935316525557) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
More about DSP56F801
The 56F801, a member of the 56800 core-based family of Digital Signal Controllers, combines the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals on a single chip to create an extremely cost-effective solution for servo and motor control, power inverter, and converter applications.
The 56800 core is based on a Harvard-style architecture consisting of three execution units which operate in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP- and MCU-style applications. The instruction set is also highly efficient for C Compilers, enabling rapid development of optimized control applications.