LPC3180FEL320 Product Information|NXP

Buy Options

LPC3180FEL320/01,5

No Longer Manufactured

12NC: 935286983551

Details

Order

LPC3180FEL320,551

No Longer Manufactured

12NC: 935281874551

Details

Order

Operating Features

ParameterValue
SCTimer / PWM
1
Temperature range
-40 °C to +85 °C
Product category
170-LPC3100/200-

Environmental

Part/12NCPbFreeEU RoHSHalogen FreeRHF IndicatorREACH SVHCWeight (mg)
LPC3180FEL320/01,5(935286983551)
Yes
Yes
Certificate Of Analysis (CoA)
Yes
DREACH SVHC
540.0
LPC3180FEL320,551(935281874551)
Yes
Yes
Yes
DREACH SVHC
302.44105063999996

Quality

Part/12NCSafe Assure Functional SafetyMoisture Sensitivity Level (MSL)Peak Package Body Temperature (PPT) (C°)FITMTBFIR
Lead Free SolderingLead SolderingLead Free Soldering
LPC3180FEL320/01,5
(935286983551)
No
3
240
260
2.84
2.58397932816537E8
0.0
LPC3180FEL320,551
(935281874551)
-
3
240
260
2.84
2.58397932816537E8
0.0

Shipping

Part/12NCHarmonized Tariff (US)Disclaimer
LPC3180FEL320/01,5
(935286983551)
854231
LPC3180FEL320,551
(935281874551)
854231

Discontinued and Replacement Part Data

Part/12NCDiscontinuance NoticeLast Time Buy DateLast Time Delivery DateReplacement
LPC3180FEL320/01,5
(935286983551)
NOTICE
2018-05-31
2018-11-30
-
LPC3180FEL320,551
(935281874551)
-
1999-01-30
1999-12-31
LPC3180FEL320/01,5
(935286983551)

Product Change Notice

Part/12NCIssue DateEffective DatePCNTitle
LPC3180FEL320/01,5
(935286983551)
2018-12-192018-12-20201711018DNU02Product Discontinuation Notice - Align SOIC EOL Dates

More about LPC3180FEL320

The LPC3180 is an ARM9-based microcontroller for embedded applications requiring high performance combined with low power dissipation. It achieves these objectives through the combination of NXP®'s state-of-the-art 90 nanometer technology with an ARM926EJ-S CPU core with a Vector Floating Point (VFP) coprocessor and a large array of standard peripherals including USB On-The-Go.

The microcontroller can operate at over 200 MHz CPU frequency (about 220 MIPS per Arm Inc.). The ARM926EJ-S CPU incorporates a 5-stage pipeline and has a Harvard architecture with separate 32 kB instruction and data caches, a demand paged MMU, DSP instruction extensions with a single cycle MAC, and Jazelle Java bytecode execution hardware. A block diagram of the microcontroller is shown .

Power optimization in this microcontroller is done through process and technology development (Intrinsic Power), and architectural means (Managed Power).

The LPC3180 also incorporates an SDRAM interface, NAND flash interfaces, USB 2.0 full-speed interface, seven UARTs, two I²C-bus interfaces, two SPI ports, a Secure Digital (SD) interface, and a 10-bit ADC in addition to many other features.

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