Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
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Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
32-bit ARM Cortex-M3 flashless MCU with security features; 200 kB SRAM; Ethernet, two HS USB, LCD, EMC
12NC: 935296282551
Details
Order
Parameter | Value |
---|---|
ADC (bits) | 10 |
ADC (Channels) | 2 |
Timer | 10 x TIM x 32 |
USB | 2 x USB |
Core: Number of cores (SPEC) | 1 |
GPIO | 164 |
Description | 32-bit ARM Cortex-M3 flashless MCU with security features; 200 kB SRAM; Ethernet, two HS USB, LCD, EMC |
Free Programmable CPU | Arm Cortex-M3 |
Supply Voltage [Min - Max] | 2.4, 3.6 |
ADC | 2 |
CAN | 2 |
Operating Frequency [Max] (MHz) | 180 |
ADC COUNT CLOUD | 2 |
Frequency (Max) (kHz) | 180000 |
Product category | 140-LPC1800- |
Supply Voltage [max] (V) | 3.6 |
Ambient Operating Temperature (Min to Max) (℃) | -40 to 105 |
Supply Voltage [min] (V) | 2.4 |
Peripherals | ADC, CAN, ETH, I²C, SENT, SPI, TIM, UART, USB |
Memory Size (B) | 200000 |
PHY | CAN |
Supply Voltage [Min to Max] (V) | 2.4 to 3.6 |
Peripheral Type | ADC, CAN, ETH, I²C, SENT, SPI, TIM, UART, USB |
ADC (bits) | 10 |
USB (speed) | HS (2x) |
Ethernet w/ 1588 | 1 |
Serial Communication | 2 x I²C, 3 x SPI, 4 x UART |
ADC [Number, bits] | 2 x 10 |
CAN Channels | 2 |
Core Type | 1 x Arm Cortex-M3 |
Number of pins | 256 |
Package Style | LBGA |
Peripheral Type | ADC, CAN, ETH, I²C, SENT, SPI, TIM, UART, USB |
SRAM (Bytes) | 200000 |
eTSEC | 26 |
TDM | 26 |
I2C | 2 |
Parameter | Value |
---|---|
J1850 | 26 |
SLIC | 26 |
Security Status | COMPANY PUBLIC |
SPI | 3 |
Timers [Number, bits] | 10 x 32 |
Temperature range | -40 °C to +85 °C |
Operating Voltage [Min to Max] (V) | 2.4 to 3.6 |
Memory | SRAM |
Core Type | Arm Cortex-M has child M3, M33, M4, M4F |
ADC Resolution | 10 |
Interfaces | Interfaces |
Internal Memory Supported | SRAM |
Timer (bits) | 32 |
Timers | 10 |
IBIZ LOADER | Arm Cortex-M3 |
CLOUD_PROD3_NXP_CLOCK_SPEED_MAX | 180 |
UART | 4 |
32-bit Timer | 10 |
Pad supply (V) | 2.4 to 3.6 |
SENT | 0 |
USB (type) | host/device |
CLOUD_PROD2_NXP_CLOCK_SPEED_MAX | 180 |
USB Controllers | 2 |
ADC sample rate | 400 ksps |
Communication protocol | ADC, CAN, ETH, I²C, SENT, SPI, TIM, UART, USB |
CLOUD PROD - Operating Frequency [Max] (MHz) | 180 |
SRAM (kB) | 200 |
SCTimer / PWM | 1 |
Core Type | Arm Cortex-M3 |
Operating Temperature (Min-Max) (℃) | -40 to 105 |
Arm Core | Arm Cortex-M3 |
Ethernet | 1 |
Independent ADC Modules | 2 |
Master Interface | ADC, CAN, ETH, I²C, SENT, SPI, TIM, UART, USB |
Controller Interface | ADC, CAN, ETH, I²C, SENT, SPI, TIM, UART, USB |
Operating Frequency [Max] (MHz) | 180 |
Part/12NC | PbFree | EU RoHS | Halogen Free | RHF Indicator | REACH SVHC | Weight (mg) |
---|---|---|---|---|---|---|
LPC18S50FET256,551(935296282551) | Yes | Yes Certificate Of Analysis (CoA) | Yes | REACH SVHC | 740.54533981 |
Part/12NC | Safe Assure Functional Safety | Moisture Sensitivity Level (MSL) | Peak Package Body Temperature (PPT) (C°) | ||
---|---|---|---|---|---|
Lead Free Soldering | Lead Soldering | Lead Free Soldering | |||
LPC18S50FET256,551 (935296282551) | No | 3 | 240 | 260 |
Part/12NC | Harmonized Tariff (US)Disclaimer | Export Control Classification Number (US) |
---|---|---|
LPC18S50FET256,551 (935296282551) | 854231 | 5A992 |
Part/12NC | Issue Date | Effective Date | PCN | Title |
---|---|---|---|---|
LPC18S50FET256,551 (935296282551) | 2018-03-17 | 2018-06-25 | 201801009F01 | LPC18xx LPC43xx BGA Package Cu Wire Qualification for NXP-ATKH |
The LPC18S50FET256 is a Arm Cortex-M3 based microcontroller with security features for embedded applications. The Arm Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration.
The LPC18S50FET256 operates at CPU frequencies of up to 180 MHz. The Arm Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The Arm Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.
The LPC18S50FET256 includes 200 kB of on-chip SRAM, security features with AES engine, a quad SPI Flash Interface (SPIFI), a State Configurable Timer/PWM (SCTimer/PWM) subsystem, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals.