Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
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Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
12NC: 935304121551
Details
Order
Parameter | Value |
---|---|
Operating Frequency [Max] (MHz) | 180 |
GPIO | 83 |
CAN | 2 |
UART | 4 |
I2C | 2 |
SPI | 3 |
ADC (Channels) | 2 |
ADC (bits) | 10 |
Parameter | Value |
---|---|
ADC sample rate | 400 ksps |
Timers | 10 |
Timer (bits) | 32 |
SCTimer / PWM | 1 |
Temperature range | -40 °C to +85 °C |
Supply Voltage [min] (V) | 2.4 |
Supply Voltage [max] (V) | 3.6 |
Product category | 140-LPC1800- |
Part/12NC | PbFree | EU RoHS | Halogen Free | RHF Indicator | REACH SVHC | Weight (mg) |
---|---|---|---|---|---|---|
LPC18S10FBD144E(935304121551) | Yes | Yes Certificate Of Analysis (CoA) | Yes | REACH SVHC | 1349.747216572 |
Part/12NC | Safe Assure Functional Safety | Moisture Sensitivity Level (MSL) | Peak Package Body Temperature (PPT) (C°) | ||
---|---|---|---|---|---|
Lead Free Soldering | Lead Soldering | Lead Free Soldering | |||
LPC18S10FBD144E (935304121551) | No | 3 | 240 | 260 |
Part/12NC | Harmonized Tariff (US)Disclaimer | Export Control Classification Number (US) | CCATS |
---|---|---|---|
LPC18S10FBD144E (935304121551) | 854231 | 5A992 | G159768 |
Part/12NC | Issue Date | Effective Date | PCN | Title |
---|---|---|---|---|
LPC18S10FBD144E (935304121551) | 2018-02-02 | 2018-02-12 | 201801029I | Changing Packing Trays for Products in 14x14 and 20x20 (H)LQFP Packages. |
The LPC18S10FBD144 is a Arm Cortex-M3 based microcontroller with security features for embedded applications. The Arm Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration.
The LPC18S10FBD144 operates at CPU frequencies of up to 180 MHz. The Arm Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The Arm Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.
The LPC18S10FBD144 includes 136 kB of on-chip SRAM, security features with AES engine, a quad SPI Flash Interface (SPIFI), a State Configurable Timer/PWM (SCTimer/PWM) subsystem, an external memory controller, and multiple digital and analog peripherals.