Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
Features
QorIQ Qonverge SoC, 2x1.2GHz Starcore DSP, 2x1.6GHz e6500 CPU, MAPLE-B3 accl, encrypted, 0-105
Package
BGA1020: BGA1020, plastic, ball grid array; 1020 balls; 1 mm pitch; 33 mm x 33 mm x 2.78 mm body
Buy Options
B4420NSE7QQMD
Active
12NC: 935323499557
Details
Order
Operating Features
| Parameter | Value |
|---|---|
Core Type | SC3900, e6500 |
Core: Number of cores (SPEC) | 2, 2 |
Operating Frequency [Max] (MHz) | 1600 |
Cache (KB) | 32 |
| Parameter | Value |
|---|---|
L2 Cache (Max) (KB) | 4096 |
Ethernet Type | 2.5GBaseT, SGMII |
Ambient Operating Temperature (Min to Max) (℃) | 0 to 105 |
Environmental
| Part/12NC | PbFree | EU RoHS | Halogen Free | RHF Indicator | 2nd Level Interconnect | REACH SVHC | Weight (mg) |
|---|---|---|---|---|---|---|---|
B4420NSE7QQMD(935323499557) | Yes | Yes Certificate Of Analysis (CoA) | Yes |  | e1 | REACH SVHC | 7097.3 |
Quality
| Part/12NC | Safe Assure Functional Safety | Moisture Sensitivity Level (MSL) | Peak Package Body Temperature (PPT) (C°) | Maximum Time at Peak Temperatures (s) | |||
|---|---|---|---|---|---|---|---|
| Lead Free Soldering | Lead Free Soldering | Lead Free Soldering | |||||
B4420NSE7QQMD (935323499557) | No | 3 | 250 | 30 | |||
Shipping
| Part/12NC | Harmonized Tariff (US)Disclaimer | Export Control Classification Number (US) | CCATS |
|---|---|---|---|
B4420NSE7QQMD (935323499557) | 854231 | 5A002A1 | G140974 |
Product Change Notice
| Part/12NC | Issue Date | Effective Date | PCN | Title |
|---|---|---|---|---|
B4420NSE7QQMD (935323499557) | 2025-04-16 | 2025-05-26 | 202504006I | Freescale Logo to NXP Logo Product Marking Conversion for All Remaining Former Freescale Products |
B4420NSE7QQMD (935323499557) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
More about B4420
QorIQ® Qonverge B4420 multicore system-on-chip (SoC) architecture is designed for high-performance wireless infrastructure applications. It provides ultra-high-performance for carrier-grade metrocell and microcell base station platforms supporting various wireless standards including WCDMA (HSPA/HSPA+), FDD-LTE, TDD-LTE and LTE-Advanced including 3GPP LTE Rel. 10/11.
This multicore SoC includes four programmable cores, two 64-bit Power Architecture® cores and two cores based on a StarCore® flexible vector processor (FVP) and high throughput, low latency hardware accelerators for Layer-1, Layer-2 and Transport to enable highly optimized processing for the radio processing chain from PHY to Transport layers.