The FRCC2100 is the FlexRay Communication Controller synthesizable IP core from NXP, the world’s leading supplier of semiconductor devices for the automotive industry. A founding member of the FlexRay Consortium, NXP produced the first automotive-qualified FlexRay controller devices and provided the FlexRay controller IP for the first production vehicle to feature FlexRay technology—the BMW X5.
The FRCC2100 fully complies with FlexRay Communication System Protocol Specification, Version 2.1, Revision A. It implements the specification-defined Controller Host Interface (CHI) and Protocol Engine (PE) functionality, with clean partitioning between the CHI and PE functional blocks.
The FRCC2100 supports 4–252 message buffers and features standard interfaces to system logic and memories, so it can be readily optimized to your system requirements and easily integrated into your FPGA or ASIC device.
The host CPU interface is similar to the AMBA 2 APB. Example glue logic to connect to AMBA 2 APB is included with the product. The interface to FlexRay memory, which stores the message buffer header, payload, and status, is AMBA 2 AHB and can be adapted to other system memory interfaces upon request.
A rich ecosystem, including support from leading FlexRay software providers and a starter kit available for evaluation and prototyping, enables rapid software development.
Partner Silvaco takes care of the distribution of FlexRay Communication Controller synthesizable IP core. Silvaco is a leading EDA provider of Software tools, used in analog/mixed-signal, power IC and memory design.
Headquartered in Santa Clara, California, Silvaco has a global presence with offices located in North America, Europe, Japan and Asia for over 30 years and is offering fast-turnaround and affordable services for TCAD, SPICE Modeling, and PDK development. In June 2016 Silvaco acquired Semiconductor IP blocks vendor IPextreme, now the IP department of Silvaco (under IPextreme brand)
The USB IP is owned by NXP, but packaged, sold, and supported through Silvaco
Gate count and performance
| Number of message buffers | gates | Minimal Chi Frequency |
| 4 | 76,720 | 20 |
| 32 | 83,431 | 22 |
| 252 | 140,997 | 135 |
| Option | Range | Default |
| Maximum number of message buffers | 4-252 | 32 |
| FlexRay memory (AHB) data bus width | 32 or 64 (bits) | 32 |
| FRCC2100 Deliverables | |
| Synthesizable Verilog source code | |
| Integration testbench and tests | |
| Documentation | |
| Automatic configuration through the IPextreme IP distribution and support portal | |
| Scripts for simulation and synthesis with support for common EDA tools |