NXP’s e200 family of synthesizable, high-efficiency cores is intended for cost-sensitive, embedded real-time applications with significant performance requirements. The four e200 cores —e200z0, e200z1, e200z3, and e200z6—provide a range of features ideal for automotive, avionics, robotics, industrial control, medical devices, and compact networking applications.
Built to Power Instruction Set Architecture (ISA) Version 2.03, all four cores support variable length encoding (VLE); all except the z0 also implement the full 32-bit Book E instruction set. The cores offer low interrupt latency, AMBA AHB connectivity, and low-power design through clock gating. Debug features include static debug through Nexus Class 1 and real time debug through Nexus Class 2/3.
The small-footprint z0 core has a compact four-stage pipeline and runs the VLE instruction set, which delivers excellent code density. Reduced memory requirements and compact design make the z0 ideal for low-cost applications.
In addition to running the full 32-bit and VLE instruction sets, the z1 and z3 feature a memory management unit (MMU) for full operating system support. For applications with significant signal processing requirements, the z3 also includes a signal-processing engine (SPE) and single-precision floating-point unit (FPU), which often eliminates the need for an additional DSP.
The z6 is the highest-performance core of the family, with a seven-stage pipeline machine, all of the features of the z3, plus an integrated cache unit.
The z1 core is ideal for cost-sensitive applications that require an MMU but do not need enhanced DSP support.
The z0 core is intended for low-end cacheless MCU implementations that do not require an MMU and can benefit from very compact code.
Partner Silvaco takes care of the distribution of e200 family of synthesizable. Silvaco is a leading EDA provider of Software tools, used in analog/mixed-signal, power IC and memory design.
Headquartered in Santa Clara, California, Silvaco has a global presence with offices located in North America, Europe, Japan and Asia for over 30 years and is offering fast-turnaround and affordable services for TCAD, SPICE Modeling, and PDK development. In June 2016 Silvaco acquired Semiconductor IP blocks vendor IPextreme, now the IP department of Silvaco (under IPextreme brand)
The USB IP is owned by NXP, but packaged, sold, and supported through Silvaco
Each of the NXP e200 Power Architecture cores is in technology-independent RTL source code format and includes:
For detailed information on deliverables, please contact us: