The FlexCAN controller is a highly configurable, synthesizable core implementing the CAN protocol (ISO 11898-1), CAN with Flexible Data rate (CAN FD), and CAN 2.0 B protocol specifications, built from silicon-proven technology from NXP Semiconductors.
FlexCAN Controller
Features
- Full implementation of CAN FD and CAN 2.0 B
- Compliant with ISO 11898-1
- Flexible mailboxes configurable
- Individual Rx mask register per mailbox
- Full featured Rx FIFO, stores up to 6 frames
- Transmission abort capability
- Listen-only mode
- Loop-back mode supporting self-test operation
- Programmable transmission priority scheme
- Time stamp based on 16-bit free-running timer with an optional external time tick
- Low power modes with programmable wake-up on bus activity or matching with received frames (pretended networking)
- Transceiver delay compensation for CAN FD Tx at faster data rates
- Detection and correction of memory read (ECC)
- SystemVerilog integration testbench including a number of usage scenarios
Partner Silvaco takes care of the distribution of FlexCAN controller. Silvaco is a leading EDA provider of Software tools, used in analog/mixed-signal, power IC and memory design.
Headquartered in Santa Clara, California, Silvaco has a global presence with offices located in North America, Europe, Japan and Asia for over 30 years and is offering fast-turnaround and affordable services for TCAD, SPICE Modeling, and PDK development. In June 2016 Silvaco acquired Semiconductor IP blocks vendor IPextreme, now the IP department of Silvaco (under IPextreme brand)
The USB IP is owned by NXP, but packaged, sold, and supported through Silvaco
Options
| Option | Range |
| IRMQ_EN | Yes or No |
| LOCK_IRMQ | Yes or No |
| ECC_EN | Yes or No |
| DMA_EN | Yes or No |
| PNET_EN | Yes or No |
| FD_EN | Yes or No |
| NUMBER_OF_MB | 16, 32, 64, 96, 128 |
Deliverables
| Verilog RTL source code |
| Test bench with test suites |
| Documentation including User's Guide and Integration Guide |
| Technology-independent synthesis constraints |