The PowerQUICC® II™ integrated communications processor family delivers excellent integration of processing power for networking and communications peripherals, providing customers with an innovative, total system solution for building high-end communications systems. NXP® Semiconductors's PowerQUICC II processor family is the next generation of the leading PowerQUICC™ line of integrated communications processors, providing higher performance in all areas of device operation, including greater flexibility, extended capabilities, and higher integration.
Our leading PowerQUICC architecture integrates two processing blocks. One block is a high-performance embedded G2 core and the second block is the Communications Processor Module (CPM). The CPM of the PowerQUICC II processor can support up to three fast serial communications controllers (FCCs), two multichannel controllers (MCCs), four serial communications controllers (SCCs), two serial management controllers (SMCs), one serial peripheral interface (SPI) and one I²C interface. The combination of the G2 core and the CPM, along with the versatility and performance of the PowerQUICC II processor family, provides customers with enormous potential in developing networking and communications products while significantly reducing time-to-market development stages.
| 8250 | 8255 | 8260 | 8264 | 8265 | 8266 | |
|---|---|---|---|---|---|---|
| IMA Functionality | - | - | - | Yes | - | Yes |
| UTOPIA II Ports | 0 | 2 | 2 | 2 | 2 | 2 |
| PCI Interface | Yes | - | - | - | Yes | yes |
| Multi-Channel HDLC | Up to 128 | Up to 128 | Up to 256 | Up to 256 | Up to 256 | Up to 256 |
| I-Cache (Kbyte) | 16 | 16 | 16 | 16 | 16 | 16 |
| Fast Communication Controllers (FCCs) | 3 | 2 | 3 | 3 | 3 | 3 |
| Serial Communications Controllers (SCCs) | 4 | 4 | 4 | 4 | 4 | 4 |
| D-Cache (Kbyte) | 16 | 16 | 16 | 16 | 16 | 16 |
| Ethernet (10/100) | Up to 3 | Up to 2 | Up to 3 | Up to 3 | Up to 3 | Up to 3 |
| Ethernet (10T) | Up to 4 | Up to 4 | Up to 4 | Up to 4 | Up to 4 | Up to 4 |
| IMMR_ [16-31]¹ | Rev_Num² | Qualification | Revision | Process | Mask | |
|---|---|---|---|---|---|---|
| MPC8260 Family | XC | A.1 B.3 C.2 |
0.29 µm (HiP3) |
0K26N 3K23A 6K23A, 7K23A |
||
| MPC8260 Family | XC MC MC |
A.0 B.1 C.0 |
0.25 µm (HiP4) |
2K25A 4K25A 5K25A |
||
| MPC8280 Family | - MC MC |
0 0.1 A.0 |
0.13 µm (HiP7) |
0K49M 1K49M 2K49M, 3K49M |
||
| MPC8272 Family | PC MC |
0 A.0 |
0.13 µm (HiP7) |
0K50M 1K50M |
Notes:
1. The IMMR[16-31] indicates the mask number.
2. The Rev_Num located at offset 0x8AF0 in DPRAM indicates the CPM microcode revision number.
3 . Encryption Enabled.
4 . Encryption Disabled.
Masks and versions table last updated on 14OCT2004.
Quick reference to our documentation types.
1-5 of 46 documents
2 design files
2 hardware offerings
Quick reference to our software types.
2 software files
Note: For better experience, software downloads are recommended on desktop.
To get further assistance directly from NXP, please see our Engineering Services.
1-5 of 7 engineering services
To find additional partner offerings that support this product, visit our Partner Marketplace.
.png)