P5020NXE7TNB Product Information|NXP

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P5020NXE7TNB

End of Life

12NC: 935325757557

Details

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Operating Features

ParameterValue
Core Type
e5500
Core: Number of cores (SPEC)
2
Operating Frequency [Max] (MHz)
1800
ParameterValue
PCIe
4
External Memory Supported
DDR3 SDRAM, DDR3L SDRAM

Environmental

Part/12NCPbFreeEU RoHSHalogen FreeRHF Indicator2nd Level InterconnectREACH SVHCWeight (mg)
P5020NXE7TNB(935325757557)
Yes
Yes
Certificate Of Analysis (CoA)
Yes
D
e1
REACH SVHC
13973.9

Quality

Part/12NCSafe Assure Functional SafetyMoisture Sensitivity Level (MSL)Peak Package Body Temperature (PPT) (C°)Maximum Time at Peak Temperatures (s)
Lead Free SolderingLead Free SolderingLead Free Soldering
P5020NXE7TNB
(935325757557)
No
3
245
30

Shipping

Part/12NCHarmonized Tariff (US)DisclaimerExport Control Classification Number (US)CCATS
P5020NXE7TNB
(935325757557)
854231
5A002A1
G144423

Discontinued and Replacement Part Data

Part/12NCDiscontinuance NoticeLast Time Buy DateLast Time Delivery DateReplacement
P5020NXE7TNB
(935325757557)
NOTICE
2020-03-30
2020-09-30
-

Product Change Notice

Part/12NCIssue DateEffective DatePCNTitle
P5020NXE7TNB
(935325757557)
2020-12-152020-12-16202011011INXP Will Add a Sealed Date to the Product Label
P5020NXE7TNB
(935325757557)
2019-09-252019-09-26201909022DNDiscontinuance Notice for DSP56303 68360 PBGA only 8569 P5020 8272 Family Lead only 8313 Family Lead only

More about P5020

The dual-core P5020 and single-core P5010 processors deliver 64-bit processing, based on the e5500 core built on Power Architecture® technology. With frequencies scalable to 2.0 GHz, large caches and high per-cycle efficiency, these products target control plane and computer applications that require high single-threaded performance.

The P5 platform leverages architectural features pioneered in the P4 platform, including the three-level cache hierarchy for low latencies, hardware hypervisor for robust virtualization support, data path acceleration architecture (DPAA) for offloading packet handling tasks from the core and the CoreNet® switch fabric that eliminates internal bottlenecks. This enables architectural compatibility from the P5 platform to the P4 platform as well as to the P3 platform.