Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
Features
QorIQ, 64-Bit Power Arch SoC, 2.0GHz, DDR3, PCIe, GbE, SRIO, HW Accel, 0 to 105C Rev 2.0
Package
BGA1295: plastic, ball grid array; 1295 bumps; 1.0 mm pitch; 37.5 mm x 37.5 mm x 3.19 mm body
Buy Options
P5010NSN7VNB
End of Life
12NC: 935321935557
Details
Order
Operating Features
| Parameter | Value |
|---|---|
Security Status | COMPANY PUBLIC |
Description | QorIQ, 64-Bit Power Arch SoC, 2.0GHz, DDR3, PCIe, GbE, SRIO, HW Accel, 0 to 105C Rev 2.0 |
| Parameter | Value |
|---|---|
Number of pins | 1295 |
Package Style | BGA |
Environmental
| Part/12NC | PbFree | EU RoHS | Halogen Free | RHF Indicator | 2nd Level Interconnect | REACH SVHC | Weight (mg) |
|---|---|---|---|---|---|---|---|
P5010NSN7VNB(935321935557) | Yes | Yes Certificate Of Analysis (CoA) | Yes |  | e1 | REACH SVHC | 13973.9 |
Quality
| Part/12NC | Safe Assure Functional Safety | Moisture Sensitivity Level (MSL) | Peak Package Body Temperature (PPT) (C°) | Maximum Time at Peak Temperatures (s) | |||
|---|---|---|---|---|---|---|---|
| Lead Free Soldering | Lead Free Soldering | Lead Free Soldering | |||||
P5010NSN7VNB (935321935557) | No | 3 | 245 | 30 | |||
Shipping
| Part/12NC | Harmonized Tariff (US)Disclaimer | Export Control Classification Number (US) |
|---|---|---|
P5010NSN7VNB (935321935557) | 854231 | 3A991A1 |
Discontinued and Replacement Part Data
| Part/12NC | Discontinuance Notice | Last Time Buy Date | Last Time Delivery Date |
|---|---|---|---|
P5010NSN7VNB (935321935557) | - | 2018-03-01 | 2020-06-01 |
Product Change Notice
| Part/12NC | Issue Date | Effective Date | PCN | Title |
|---|---|---|---|---|
P5010NSN7VNB (935321935557) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
More about P5020
The dual-core P5020 and single-core P5010 processors deliver 64-bit processing, based on the e5500 core built on Power Architecture® technology. With frequencies scalable to 2.0 GHz, large caches and high per-cycle efficiency, these products target control plane and computer applications that require high single-threaded performance.
The P5 platform leverages architectural features pioneered in the P4 platform, including the three-level cache hierarchy for low latencies, hardware hypervisor for robust virtualization support, data path acceleration architecture (DPAA) for offloading packet handling tasks from the core and the CoreNet® switch fabric that eliminates internal bottlenecks. This enables architectural compatibility from the P5 platform to the P4 platform as well as to the P3 platform.