Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
Sign in for a personalized NXP experience.
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
12NC: 935287118551
Details
Order
Part/12NC | PbFree | EU RoHS | Halogen Free | RHF Indicator | REACH SVHC | Weight (mg) |
---|---|---|---|---|---|---|
LPC2929FBD144,551(935287118551) | Yes | Yes Certificate Of Analysis (CoA) | Yes | REACH SVHC | 1276.5081372000002 |
Part/12NC | Safe Assure Functional Safety | Moisture Sensitivity Level (MSL) | Peak Package Body Temperature (PPT) (C°) | FIT | MTBF | IR | ||
---|---|---|---|---|---|---|---|---|
Lead Soldering | Lead Free Soldering | Lead Soldering | Lead Free Soldering | |||||
LPC2929FBD144,551 (935287118551) | No | 2 | 2 | 225 | 260 | 2.84 | 2.58397932816537E8 | 0.0 |
Part/12NC | Harmonized Tariff (US)Disclaimer | Export Control Classification Number (US) |
---|---|---|
LPC2929FBD144,551 (935287118551) | 854231 | 3A991A2 |
Part/12NC | Issue Date | Effective Date | PCN | Title |
---|---|---|---|---|
LPC2929FBD144,551 (935287118551) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
LPC2929FBD144,551 (935287118551) | 2018-02-02 | 2018-02-12 | 201801029I | Changing Packing Trays for Products in 14x14 and 20x20 (H)LQFP Packages. |
The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies of up to 125 MHz, Full-speed USB 2.0 OTG and device controller, CAN and LIN, 56 kB SRAM, up to 768 kB flash memory, external memory interface, three 10-bit ADCs, and multiple serial and parallel interfaces in a single chip targeted at consumer, industrial and communication markets. To optimize system power consumption, the LPC2926/2927/2929 has a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling.