Application Note (1)
-
A metastability primer[AN219]
Sign in for a personalized NXP experience.
The SSTUB32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated as Register A or Register B on the DIMM.
The SSTUB32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit.
The SSTUB32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm × 5.5 mm).
1 result
Exclude 1 NRND
Part | CAD Model | Status | Package Type |
---|---|---|---|
No Longer Manufactured | LFBGA96 |
SSTUB32866EC
Quick reference to our documentation types.
3 documents
Compact List
There are no results for this selection.
Please wait while your secure files are loading.
3 documents
Compact List
Receive the full breakdown. See the product footprint and more in the eCad file.
Help us improve your experience on our site. We invite you to take our five-question survey.