Multi-Channel PCIe Gen 4 Linear Equalizer

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Block Diagram

PTN3944 Block Diagram

PTN3944 Block Diagram

Features

System Features

  • Supports PCIe Gen1 (2.5 Gbps) x4, Gen2 (5 Gbps) x4, Gen3 (8 Gbps) x4, and Gen4 (16 Gbps) x4
    • Peaking gain up to 18.3 dB at 8 GHz
    • Output swing linearity control: 500 mVppd to 950 mVppd
    • Flat gain of +0.7 dB or -0.7 dB
  • Configurable via I²C interface (supports 16 target addresses)
  • Supports maximum voltage limit (Vvoltage_jump) to align to the latest system platform capabilities
  • Integrated termination resistors provide impedance matching on both transmit and receive sides
  • RX equalizers on all high-speed channels to compensate for signal attenuation
  • Good linearity over the frequency band (DC to Nyquist frequency) and input voltage dynamic range
  • Differential input/output return loss performance < -15 dB up to 8 GHz
  • Flow-through pin-out to ease PCB layout and minimize crosstalk effects
    • Very low crosstalk: DDNEXT < -60 dB up to 8 GHz
    • Very low crosstalk: DDFEXT < -50 dB up to 8 GHz
  • Low active current consumption for output swing linearity control of 950 mVppd
    • Single channel: 62 mA (typ)
    • Two channels: 125 mA (typ)
    • Four channels: 250 mA (typ)
  • Power Supply 1.7 V to 1.9 V
  • Small high performance HWFLGA36 package
  • ESD HBM 1.5 kV, CDM 1 kV
  • Operating temperature range -20 °C to +85 °C

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Documentation

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3 documents

Design Files

Hardware

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