QorIQ® P1020 and P1011 Dual- and Single-Core Communications Processors

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Block Diagram

Freescale QorIQ P1020/11 Communication Processor Block Diagram

Freescale QorIQ P1020/11 Communication Processor Block Diagram

Features

Core Complex

  • Dual (P1020) or single (P1011) high-performance Power Architecture® e500 cores, 32 KB L1 cache, up to 800 MHz
  • 256 KB L2 cache with ECC, also configurable as SRAM and stashing memory

Networking Elements

  • Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSEC)
  • Two SGMII interfaces
  • Support for IEEE® 1588

Accelerators and Memory Control

  • DDR2/3 32-bit memory controller with ECC support
  • Integrated security engine
    • Protocol support includes SNOW, ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS, Kasumi
    • XOR acceleration

Basic Peripherals and Interconnect

  • Four-lane SERDES up to 3.125 GHz multiplexed across controllers
  • Two PCI Express® Gen1.0 interface controllers
  • Two USB2.0 controllers
  • Enhanced Local Bus Controller (eLBC)
  • TDM
  • eSDHC
  • Dual I²C, DUART, PIC, DMA, GPIO

Additional Features

Comparison Table

P1011 P1012 P1020 P1021
Cores 1 1 2 2
Core Frequency 533 - 800 MHz 533 - 800 MHz 533 - 800 MHz 533 - 800 MHz
L2 Cache 256KB 256KB 256KB 256KB
DDR 32-bit DDR2/DDR3 32-bit DDR2/DDR3 32-bit DDR2/DDR3 32-bit DDR2/DDR3
GbE 3 x 10/100/1000 3 x 10/100/1000 3 x 10/100/1000 3 x 10/100/1000
PCIe Gen 1.0 2 controllers w/ 4 SERDES 2 controllers w/ 4 SERDES 2 controllers w/ 4 SERDES 2 controllers w/ 4 SERDES
USB 2.0 2 1 2 2
Memory Card SD/MMC SD/MMC SD/MMC SD/MMC
Other interfaces SPI, 2xI²C, DUART SPI, 2xI²C, DUART SPI, 2xI²C, DUART SPI, 2xI²C, DUART
TDM or QUICC Engine TDM QUICC Engine TDM QUICC Engine
Accelerators SEC3.3 SEC3.3 SEC3.3 SEC3.3

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Documentation

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Software

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