Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
Features
1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for DDR2 RDIMM applications
Package
LFBGA96: plastic, low profile fine-pitch ball grid array package; 96 balls; 0.8 mm pitch; 13.5 mm x 5.5 mm x 1.5 mm body
Buy Options
SSTU32866EC,518
No Longer Manufactured
12NC: 935275071518
Details
Order
SSTU32866EC,551
No Longer Manufactured
12NC: 935275071551
Details
Order
SSTU32866EC,557
No Longer Manufactured
12NC: 935275071557
Details
Order
SSTU32866EC/G,518
No Longer Manufactured
12NC: 935275473518
Details
Order
SSTU32866EC/G,551
No Longer Manufactured
12NC: 935275473551
Details
Order
SSTU32866EC/G,557
No Longer Manufactured
12NC: 935275473557
Details
Order
Operating Features
| Parameter | Value |
|---|---|
tpd (ns) | 1.4~1.8 |
Tamb (°C) | 0~+70 |
Environmental
| Part/12NC | PbFree | EU RoHS | Halogen Free | RHF Indicator | REACH SVHC |
|---|---|---|---|---|---|
SSTU32866EC,518(935275071518) | No | No | - | REACH SVHC | |
SSTU32866EC,551(935275071551) | No | No | - |  | REACH SVHC |
SSTU32866EC,557(935275071557) | No | No | - | REACH SVHC | |
SSTU32866EC/G,518(935275473518) | Yes | Yes | No |  | REACH SVHC |
SSTU32866EC/G,551(935275473551) | Yes | Yes | No | | REACH SVHC |
SSTU32866EC/G,557(935275473557) | No | No | - | REACH SVHC |
Quality
| Part/12NC | Safe Assure Functional Safety | Moisture Sensitivity Level (MSL) | Peak Package Body Temperature (PPT) (C°) | ||
|---|---|---|---|---|---|
| Lead Soldering | Lead Free Soldering | Lead Soldering | Lead Free Soldering | ||
SSTU32866EC,518 (935275071518) | - | - | - | - | - |
SSTU32866EC,551 (935275071551) | - | 2 | 2 | 240 | 260 |
SSTU32866EC,557 (935275071557) | - | - | - | - | - |
SSTU32866EC/G,518 (935275473518) | - | - | 2 | 240 | 260 |
SSTU32866EC/G,551 (935275473551) | - | - | 2 | 240 | 260 |
SSTU32866EC/G,557 (935275473557) | - | - | - | - | - |
Shipping
| Part/12NC | Harmonized Tariff (US)Disclaimer |
|---|---|
SSTU32866EC,518 (935275071518) | 854239 |
SSTU32866EC,551 (935275071551) | 854239 |
SSTU32866EC,557 (935275071557) | 854239 |
SSTU32866EC/G,518 (935275473518) | 854239 |
SSTU32866EC/G,551 (935275473551) | 854239 |
SSTU32866EC/G,557 (935275473557) | 854239 |
Discontinued and Replacement Part Data
| Part/12NC | Discontinuance Notice | Last Time Buy Date | Last Time Delivery Date | Replacement |
|---|---|---|---|---|
SSTU32866EC,518 (935275071518) | - | 2008-06-30 | 2008-06-30 | SSTU32866EC/G,518 (935275473518) |
SSTU32866EC,551 (935275071551) | - | 2008-06-30 | 2008-06-30 | SSTU32866EC/G,551 (935275473551) |
SSTU32866EC,557 (935275071557) | - | 2008-06-30 | 2008-06-30 | SSTU32866EC/G,557 (935275473557) |
SSTU32866EC/G,518 (935275473518) | - | 2005-06-30 | 2005-12-31 | SSTUB32866EC/G,518 (935281279518) |
SSTU32866EC/G,551 (935275473551) | - | 2005-06-30 | 2005-12-31 | SSTUB32866EC/G,518 (935281279518) |
SSTU32866EC/G,557 (935275473557) | - | 2005-06-30 | 2005-12-31 | SSTUB32866EC/G,518 (935281279518) |
More about SSTU32866EC
Archived content is no longer updated and is made available for historical reference only.
The SSTU32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity checking function in a compatible pinout. The JEDEC standard for SSTU32866 is pending publication. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1:1 or 14-bit 1:2, and in the latter configuration can be designated as Register A or Register B on the DIMM.
The SSTU32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active-LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit.
The SSTU32866 is packaged in a 96-ball, 6 x 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm by 5.5 mm).