1
Out of the Box2
Get to Know the Hardware3
Install Software4
Configuring the Hardware for StartupSign in to save your progress. Don't have an account? Create one.
NXP analog product development boards provide an easy-to-use platform for evaluating NXP products. The boards support a range of analog, mixed-signal and power solutions. They incorporate monolithic integrated circuits and system-in-package devices that use proven high-volume technology. NXP products offer longer battery life, a smaller form factor, reduced component counts, lower cost and improved performance in powering state-of-the-art systems.
This page will guide you through the process of setting up and using the KITFS86TRKFRDMEM board.
The KITFS86TRKFRDMEM kit contents include:
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In addition to the kit contents, the following hardware is necessary or beneficial when working with this kit.
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This reference design requires a Windows PC workstation. Meeting these minimum specifications should produce great results when working with this evaluation board.
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Installing software is necessary to work with this evaluation board. All listed software is available on the evaluation board's information page at the evaluation board design page or on the NXP GUI for Automotive PMIC Families.
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The KITFS86TRKFRDMEM is a hardware evaluation tool that allows performance test. The FS8600 family can be evaluated with this board because it is populated with a superset part. The PFS8613xMDA0ES part soldered on the board can be fused twice.
An external LDO provides SUP_I2C voltage with a choice of 1.8 V or 3.3 V (default). SUP_I2C is intended to power FS86 I2C communication. From USB voltage, an external DC-DC generates the OTP programming voltage (8.0 V) without any need for an external power supply.
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Figure 1 identifies important components on the board and Table 1 provides additional details on these components.
Figure 1. Evaluation board featured components location
Table 1. Evaluation board featured components location
Number | Description |
---|---|
1 | LDO1/LDO2 power supply |
2 | BUCK/BOOST power supply |
3 | VBAT Jack connector |
4 |
VBAT three position switch
|
5 | VBAT Phoenix connector |
6 | VPRE power supply |
7 | USB connectors (Open SDA for MCU flash; KL25Z for NXP GUI control) |
8 | Debug connectivity. Access to FS8600 signals |
9 | External regulator connectors (to VMONx) |
10 | VMONx configuration (Choice between monitoring a regulator or a fixed 0.8 V) |
11 | OTP mode switch |
12 | DBG pin to 0 V if unplugged |
13 | Wake1 switch |
14 | VPRE compensation network settings (455 kHz or 2.22 MHz) |
15 | VDDI2C selection |
16 | KL25Z Freedom board connectors |
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The Freedom KL25Z is an ultra low-cost development platform for Kinetis L series MCU built on Arm Cortex-M0+ processor.
Figure 2. Freedom development platform
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The device configuration can be programmed twice and emulated indefinitely using the GUI.
Device programming and emulation steps are described in the NXP GUI for FS86 Automotive Family User Manual available at NXP GUI for Automotive PMIC Families.
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The device configuration can be changed twice. The programming steps are described in the NXP GUI for FS86 Automotive Family User Manual available at NXP GUI for Automotive PMIC Families.
Figure 3 presents a typical hardware configuration incorporating the development board, power supply and Windows PC workstation.
Figure 3. Typical initial configuration
To configure the hardware and workstation as illustrated in Figure 3, complete the following procedure:
Table 2. Hardware configuration
Switch | Configuration | ||
---|---|---|---|
Normal mode | Debug mode entry | OPT mode entry | |
Operation | watchdog 2 s window | watchdog window fully open | OTP emulation / programming and debug mode entry |
J7 (DBG) | open | connect 1 to 2 DBG pin voltage pulled to 4.5 V or 8.0 V (SW3) | |
SW1 (WAKE1) | close (WAKE1 high) | ||
SW2 (VBAT) | middle position (VBAT OFF) | ||
SW3 (DBG_OTP) | open (DBG = 4.5 V) | close (OTP mode ON) |
J6
)
SW2
in TOP positionAt this step, if the product is in OTP mode entry configuration, all regulators are off. The user can power up with an OTP configuration or configure the mirror registers before powering up. Power-up starts as soon as one of these four actions occurs:
J7
jumper is removedSW3
is switched offSomething went wrong! Please try again.
In addition to our FS86: Safety System Basis Chip For Domain Controller, Fit For ASIL B and D page, you may also want to visit:
Application pages: