Quad 6-Bit Multiplexed I²C-Bus EEPROM DIP Switch

Block Diagram

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PCA9561

PCA9561 Block Diagram

PCA9561D, PCA9561PW

Features

Key Features

  • Selection of non-volatile register_n as source to MUX_OUT pins via I2C-bus
  • I2C-bus can override MUX_SELECT pin in selecting output source
  • 6-bit 5-to-1 multiplexer DIP switch
  • Four internal non-volatile registers
  • Internal non-volatile registers programmable and readable via I2C-bus
  • Six open-drain multiplexed outputs
  • 400 kHz maximum clock frequency
  • Operating supply voltage 3.0 V to 3.6 V
  • 5 V and 2.5 V tolerant inputs/outputs
  • Useful for Speed Step configuration of laptop computer
  • Two address pins, allowing up to four devices on the I2C-bus
  • MUX_IN values readable via I2C-bus
  • ESD protection exceeds 200 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JESDEC Standard JESD78 which exceeds 100 mA

Part numbers include: PCA9561PW.

Key Parametrics

  • Status
    End of Life
  • Budgetary Price ($US)
    0.6738
  • Operating Temperature (Min-Max) (℃)
    0 to 70
  • Failures in time
    2
  • Mean time between failures
    500000000
  • # of Addresses
    4
  • Peripheral clock frequency
    400000
  • Supply Voltage [Min to Max] (V)
    3 to 3.6
  • Number of registers
    2

Documentation

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1-5 of 9 documents

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Design Files

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2 design files

Hardware

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1 hardware offering

Engineering Services

2 engineering services

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