201801014I : PCF85063A Datasheet Application Recommendations

Update PCF85063A Datasheet to recommend customers not to Bias the PCF85063A device during Reflow.NXP recommends customers not to bias the PCF85063A device during reflow (e.g. if utilizing a 'coin' type battery in the assembly). While this is outside the operating max of the device (and not supported by NXP) if the customers so choose to continue to use this assembly method there must be the allowance for a full `0 V' level Power supply `reset' to re-enable the device. As a result the following PCF85063A Datasheet sections were modified:- Added note 1 for Table 40 (Limiting values[1]) recommending not to bias the PCA85063A device during reflow- Clarified section 8.2 (Control Registers) to reflect the 0-Volt condition on the VDD when biased.- Clarified section 8.2.1.3 (Software Reset) to recommend to start VDD at zero volts at power on or upon power cycling.Additionally for a condition where the SDA line is driven low (and not recovering) as a workaround NXP recommends customers to implement a S/W flow where a 9-clock pulse method is sent when such an event occurs. The following manuals generally and specifically should be referenced:- UM10204 (I2C Bus User Manual section 3.1.16)- UM10301 (Real Time Clock User Manual section 19.3)NXP also recommends tying VDD of the device and VDD of all the external pull-up resistors to the same Power Supply.As a result the following PCF85063A Datasheet sections were also modified:- Added note 2 for Table 4 recommending to tie VDD of the device and VDD of all the external pull-up resistors to the same Power Supply- Added Section 9.5.2.1 (I2C-bus error recovery technique)- Updated note 1 to Table 41 (Static characteristics) recommending a full '0V" Vdd value upon re-biasing PCF85063A device during restart condition- Updated Figure 31 (Application diagram for PCF85063A) and added figure notes 2 and 3

Reason of Change

NXP was notified of occurences where customers had observed an issue with the RTC not functioning (failing to provide 32 KHz output at CKO pin). In some of the cases the customers bias the PCF85063A device during reflow by connecting the device to a battery (and is powered) thus exposing the PCF85063A device to temperatures as high as 260C which is well in excess of the datasheet (and intended) device operating specifications.NXP had also been notified of instances where SDA was driven low and did not recover. The PCF85063A SDA Drive Low condition was found to recover when using the 9 SCL clocks method which is the recommended workaround. Tying VDD of the device and VDD of all the external pull-up resistors to the same Power Supply was also noted to mitigate occurence of the issue.- If the I2C State Machine is not initialized properly and starts from Read State SDA is driven low.- 8 SCL clocks bring the State Machine to Read Acknowledge state and SDA goes high.- 9th SCL clock and beyond will bring the State machine to an idle state.

Identification of Affected Products

Product identification does not change

Anticipated Impact

Data sheet revision: A new datasheet will be issued

These changes to the datasheet do not affect the PCF85063A product functionality.No impact on form fit function reliability or quality.

Affected Parts