201801008I : PCA85063A Datasheet SDA Driven Low Recovery

Update PCA85063A Datasheet to indicate S/W workaround for an SDA driven low condition as well as recommended Bias and Reflow conditions.For a condition where the SDA line is driven low (and not recovering) as a workaround NXP recommends customers to implement a S/W flow where a 9-clock pulse method is sent when such an event occurs. The following manuals generally and specifically should be referenced;- UM10204 (I2C Bus User Manual section 3.1.16)- UM10301 (Real Time Clock User Manual section 19.3)NXP also recommends tying VDD of the device and VDD of all the external pull-up resistors to the same Power Supply.Additionally NXP recommends customers not to bias the PCA85063A device during reflow (e.g. if utilizing a 'coin' type battery in the assembly). While this is outside the operating max of the device (and not supported by NXP) if the customers so choose to continue to use this assembly method there must be the allowance for a full `0 V' level Power supply `reset' to re-enable the device.As a result the following PCA85063A Datasheet sections were modified:- Added note 1 for Table 4 recommending to tie VDD of the device and VDD of all the external pull-up resistors to the same Power Supply- Added Section 9.5.3 (I2C-bus error recovery technique)- Added note 1 for Table 40 (Limiting values[1]) recommending not to bias the PCA85063A device during reflow- Updated note 1 to Table 41 (Static characteristics) recommending a full '0V" Vdd value upon re-biasing PCA85063A device during restart condition- Updated Figure 29 (Application diagram for PCA85063A) and added table notes 2 and 3

Reason of Change

NXP was notified of occurences where SDA was driven low and did not recover. The datasheet is being updated to provide potential workarounds as well as general design and assembly improvements.The PCA85063A SDA Drive Low condition was found to recover when using the 9 SCL clocks method. Tying VDD of the device and VDD of all the external pull-up resistors to the same Power Supply was also noted to mitigate occurence of the issue.- If the I2C State Machine is not initialized properly and starts from Read State SDA is driven low.- 8 SCL clocks bring the State Machine to Read Acknowledge state and SDA goes high.- 9th SCL clock and beyond will bring the State machine to an idle state.Also to notify customers not to bias the PCA85063A device during reflow as doing so exceeds the operating range of the device as denoted in the datasheet.

Identification of Affected Products

Product identification does not change

Anticipated Impact

Data sheet revision: A new datasheet will be issued

These changes to the datasheet do not affect the PCA85063A product functionality.No impact on form fit function reliability or quality.

Affected Parts