Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
Features
1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications
Buy Options
SSTUB32865ET/G,518
No Longer Manufactured
12NC: 935281691518
Details
Order
SSTUB32865ET/S,518
No Longer Manufactured
12NC: 935283143518
Details
Order
Operating Features
| Parameter | Value |
|---|---|
Security Status | COMPANY PUBLIC |
Function | Latches/registered drivers |
Description | 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications |
| Parameter | Value |
|---|---|
Number of pins | 160 |
Package Style | TFBGA |
Environmental
| Part/12NC | PbFree | EU RoHS | Halogen Free | RHF Indicator | REACH SVHC |
|---|---|---|---|---|---|
SSTUB32865ET/G,518(935281691518) | Yes | Yes | Yes |  | REACH SVHC |
SSTUB32865ET/S,518(935283143518) | No | No | - | REACH SVHC |
Quality
| Part/12NC | Safe Assure Functional Safety | Moisture Sensitivity Level (MSL) | Peak Package Body Temperature (PPT) (C°) | ||
|---|---|---|---|---|---|
| Lead Free Soldering | Lead Soldering | Lead Free Soldering | |||
SSTUB32865ET/G,518 (935281691518) | - | 2 | 240 | 260 | |
SSTUB32865ET/S,518 (935283143518) | - | - | - | - | |
Shipping
| Part/12NC | Harmonized Tariff (US)Disclaimer |
|---|---|
SSTUB32865ET/G,518 (935281691518) | 854239 |
SSTUB32865ET/S,518 (935283143518) | 854239 |
Discontinued and Replacement Part Data
| Part/12NC | Discontinuance Notice | Last Time Buy Date | Last Time Delivery Date | Replacement |
|---|---|---|---|---|
SSTUB32865ET/G,518 (935281691518) | - | 2005-06-30 | 2005-12-31 | SSTU32865ET/G,518 (935275433518) |
SSTUB32865ET/S,518 (935283143518) | - | 2005-06-30 | 2005-12-31 | SSTU32865ET/G,518 (935275433518) |
More about SSTUB32865ET
Archived content is no longer updated and is made available for historical reference only.
The SSTUB32865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs.
The SSTUB32865 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
It further offers added features over the JEDEC standard register in that it can be configured for normal or high output drive strength, simply by tying input pin SELDR either HIGH of LOW as needed. This allows use in different module designs varying from low to high density designs by picking the appropriate drive strength to match net loading conditions. Furthermore, the SSTUB32865 features two additional chip select inputs, which allow more versatile enabling and disabling in densely populated memory modules. Both added features (drive strength and chip selects) are fully backward compatible to the JEDEC standard register.
The SSTUB32865 is packaged in a 160-ball, 12 x 18 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which, while requiring a minimum 9 mm x 13 mm of board space, allows for adequate signal routing and escape using conventional card technology.