Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
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Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
12NC: 935275069518
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12NC: 935275069551
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12NC: 935275069557
Details
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12NC: 935275433518
Details
Order
12NC: 935275433551
Details
Order
12NC: 935275433557
Details
Order
Parameter | Value |
---|---|
tpd (ns) | 1.4~1.8 |
Tamb (°C) | 0~+70 |
Part/12NC | PbFree | EU RoHS | Halogen Free | RHF Indicator | REACH SVHC | Weight (mg) |
---|---|---|---|---|---|---|
SSTU32865ET,518(935275069518) | No | No | - | REACH SVHC | - | |
SSTU32865ET,551(935275069551) | No | No | - | REACH SVHC | - | |
SSTU32865ET,557(935275069557) | No | No | - | REACH SVHC | - | |
SSTU32865ET/G,518(935275433518) | Yes | Yes | Yes | REACH SVHC | 225.8 | |
SSTU32865ET/G,551(935275433551) | Yes | Yes | Yes | REACH SVHC | 225.8 | |
SSTU32865ET/G,557(935275433557) | Yes | Yes | Yes | REACH SVHC | 225.8 |
Part/12NC | Safe Assure Functional Safety | Moisture Sensitivity Level (MSL) | Peak Package Body Temperature (PPT) (C°) | ||
---|---|---|---|---|---|
Lead Free Soldering | Lead Soldering | Lead Free Soldering | |||
SSTU32865ET,518 (935275069518) | - | - | - | - | |
SSTU32865ET,551 (935275069551) | - | - | - | - | |
SSTU32865ET,557 (935275069557) | - | - | - | - | |
SSTU32865ET/G,518 (935275433518) | No | 2 | 240 | 260 | |
SSTU32865ET/G,551 (935275433551) | - | 2 | 240 | 260 | |
SSTU32865ET/G,557 (935275433557) | - | 2 | 240 | 260 |
Part/12NC | Harmonized Tariff (US)Disclaimer |
---|---|
SSTU32865ET,518 (935275069518) | 854239 |
SSTU32865ET,551 (935275069551) | 854239 |
SSTU32865ET,557 (935275069557) | 854239 |
SSTU32865ET/G,518 (935275433518) | 854239 |
SSTU32865ET/G,551 (935275433551) | 854239 |
SSTU32865ET/G,557 (935275433557) | 854239 |
Part/12NC | Discontinuance Notice | Last Time Buy Date | Last Time Delivery Date | Replacement |
---|---|---|---|---|
SSTU32865ET,518 (935275069518) | - | 2015-06-30 | 2015-12-31 | SSTU32865ET/G,518 (935275433518) |
SSTU32865ET,551 (935275069551) | - | 2015-06-30 | 2015-12-31 | SSTU32865ET/G,551 (935275433551) |
SSTU32865ET,557 (935275069557) | - | 2015-06-30 | 2015-12-31 | SSTU32865ET/G,557 (935275433557) |
SSTU32865ET/G,518 (935275433518) | - | 1998-01-30 | 1998-12-31 | - |
SSTU32865ET/G,551 (935275433551) | - | 1999-01-30 | 2000-03-31 | - |
SSTU32865ET/G,557 (935275433557) | - | 2002-12-31 | 2002-12-31 | - |
Archived content is no longer updated and is made available for historical reference only.
The SSTU32865 is a 1.8 V 28-bit 1:2 register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs.
The SSTU32865 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active-LOW).
The SSTU32865 is packaged in a 160-ball, 12 x 18 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which-while requiring a minimum 9 mm x 13 mm of board space-allows for adequate signal routing and escape using conventional card technology.