Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
Buy Options
PCU9661B,118
No Longer Manufactured
12NC: 935295677118
Details
Order
Operating Features
| Parameter | Value |
|---|---|
Security Status | COMPANY PUBLIC |
Description | Parallel bus to 1 channel UFm I2C-bus controller |
| Parameter | Value |
|---|---|
Number of pins | 48 |
Package Style | LQFP |
Environmental
| Part/12NC | PbFree | EU RoHS | Halogen Free | RHF Indicator | REACH SVHC | Weight (mg) |
|---|---|---|---|---|---|---|
PCU9661B,118(935295677118) | Yes | Yes | Yes |  | REACH SVHC | 181.22289800000001 |
Quality
| Part/12NC | Safe Assure Functional Safety | Moisture Sensitivity Level (MSL) | Peak Package Body Temperature (PPT) (C°) | FIT | MTBF | IR | ||
|---|---|---|---|---|---|---|---|---|
| Lead Soldering | Lead Free Soldering | Lead Soldering | Lead Free Soldering | |||||
PCU9661B,118 (935295677118) | No | 1 | 1 | 240 | 260 | 4.0 | 2.5E8 | 0.0 |
Shipping
| Part/12NC | Harmonized Tariff (US)Disclaimer |
|---|---|
PCU9661B,118 (935295677118) | 854239 |
Discontinued and Replacement Part Data
| Part/12NC | Discontinuance Notice | Last Time Buy Date | Last Time Delivery Date |
|---|---|---|---|
PCU9661B,118 (935295677118) | - | 2009-02-04 | 2009-02-04 |
More about PCU9661B
Archived content is no longer updated and is made available for historical reference only.
The PCU9661 is an advanced single mode I²C-bus controller. It is a fourth generation bus controller designed for data intensive I²C-bus data transfers. It has a transmit only transfer rate of up to 5 Mbits/s using the new Ultra Fast-mode (UFm) bus with push-pull topology. The serial channel has a generous 4352 byte data buffer which makes the PCU9661 the ideal companion to any CPU that needs to transmit and receive large amounts of serial data with minimal interruptions.
The PCU9661 is an 8-bit parallel-bus to I²C-bus protocol converter. It can be configured to communicate with up to 64 targets in one serial sequence with no intervention from the CPU. The controller also has a sequence loop control feature that allows it to automatically retransmit a stored sequence.
Its onboard oscillator and PLL allow the controller to generate the clocks for the I²C-bus and for the interval timer used in sequence looping. This feature greatly reduces CPU overhead when data refresh is required in fault tolerant applications.
An external trigger input allows data synchronization with external events. The trigger signal controls the rate at which a stored sequence is re-transmitted over the I²C-bus. Error reporting is handled at the transaction level, channel level, and controller level. A simple interrupt tree and interrupt masks allow further customization of interrupt management.
The controller parallel bus interface runs at 3.3 V and the I²C-bus I/Os logic levels are referenced to a dedicated VDD(IO) input pin with a range of 3.0 V to 5.5 V.