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This page will guide you through the process of setting up and using the KITTPLSNIFEVB tool.
The KIT-TPLSNIFEVB contents include:
Figure 1. Kit Contents
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The TPL sniffer requires only a 5.0 V with 50 mA (average) and 150 mA (peak) power supply through a USB Micro-B connector (for example, a power bank, or a USB cable connected to a computer).
To analyze the data sourced from the TPL sniffer a logic analyzer (for example, Saleae Logic Analyzer) is required along with its software.
Optionally, plug-ins and extensions to add to the Saleae Logic Analyzer software have been developed in order to decode TPL frames. For additional details, visit section 4.
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Refer to UM11650, KIT-TPLSNIFEVB tool for additional details on the featured components and board configuration.
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The KIT-TPLSNIFEVB board, also called TPL sniffer is working with a logic analyzer (preferably a Saleae Logic Analyzer) and its software to help analyze electrical transport protocol link (ETPL) signals.
Placed in any ETPL bus, it non-intrusively listens to all messages and monitors the frame traffic on the bus (the TPL sniffer works in listen mode only). The corresponding received data (in SPI format) is available on the ANALYZER output connector, to be connected to a logic analyzer and its software which provides further analysis of such data.
Overview of the KIT-TPLSNIFEVB tool
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The TPL sniffer exposes a set of connectors on two sides. One side is dedicated to the ETPL bus connection and on the other side all other connectors are present. The two sides are galvanically isolated from each other: the ETPL bus connectors are isolated from all other accessible points on the housing.
The ETPL connectors are located on one side of the housing and are marked TPL_IN and TPL_OUT with a polarity indication + and -. The correct polarity of the connection is mandatory for the proper functioning of the sniffer and, in most cases, also for the system to be sniffed.
Conversely, the terms IN and OUT are conventional and the two connectors are electrically in parallel inside the TPL sniffer. They are physically duplicated to make it easier to connect the wires in certain use cases. For example, in the case of a daisy chain, the original ETPL bus is cut and the two ends must be plugged onto the receptacles of the TPL sniffer. In other cases, for example, when the ETPL bus has only one differential end available for connection to the TPL sniffer, there is no difference between the TPL_IN and TPL_OUT connectors, as long as the polarity is respected.
As a rule, if a stub is created from the original ETPL bus, its length should be as short as possible.
Note: The two ETPL interface connectors are named J1
and J2
in the schematic diagram.
Figure 2. ETPL bus connectors
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The TPL sniffer is designed to add minimal load to the ETPL bus by default. Therefore, it does not add any termination impedance and the differential load seen from the bus is that of an input impedance of the MC33664 reflected on the high voltage side by the 1:1 ratio T1 isolation transformer.
In case an interface other than the default one is desired; some settings are possible on the PCB:
JP1
and JP2
located on the bottom side, should be closed (with a drop of
solder) in case a standard 150 Ω termination is desired.R13
(default DNP) and R14
and R15
(default 0 Ω).
Note: If the board must be modified and then powered without housing, proceed with caution.
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The side of the case opposite the ETPL connectors has all the other available connectors of the TPL sniffer.
J5
in the schematics. In some cases of use, the whole system including, for example, the TPL sniffer,
the power supply, the logic analyzer and the associated PC, could be an electrically floating block. This connector
allows, if desired, the ground potential of the system (for example, the TPL sniffer and anything else that has its
ground connected to the TPL sniffer ground) to be set to any other convenient potential, that is, the protective
earth or the vehicle chassis ground (KL31).J3
in the schematics.J4
in the schematics.Figure 3. Power and data connectors
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The data output connector (J3
) is an 8-pin 4x2 male connector used as an interface to the logic analyzer, to transfer
TPL messages converted to SPI format.
The signals are all unidirectional and their direction is from the TPL sniffer (output) to the logic analyzer (input).
The TPL sniffer is designed such that the cable connection to the logic analyzer can be relatively long, with a maximum length of 2 m, without loss of signal integrity and therefore maintaining the logic and timing information.
This statement is only true if the following two rules are both satisfied:
Failure to follow these rules does not guarantee proper operation of the TPL sniffer, unless the cable length is considerably short (< 15 cm) so that reflections in the cable can be neglected.
For signal integrity and EMI reduction, the data lines are interleaved with the ground potential with the pinout described in Table X.
The TPL sniffer data output lines and the ETPL inputs are internally protected by ESD suppression devices. Nevertheless, standard electrostatic precautions should be taken when handling and using the TPL sniffer.
The pin assignment for the data output connector is described in the following table:
Table 1. ANALYZER connector (J3
) pin assignment
Pin | Signal | Description |
---|---|---|
1 | INTB | SPI interrupt signal |
2 | GND | Ground |
3 | RXCLK | SPI bus clock |
4 | GND | Ground |
5 | RXDATA | SPI bus data |
6 | GND | Ground |
7 | RXCSB | SPI chip select |
8 | GND | Ground |
Figure 4. ANALYZER connector pinout
The supplied 8-pin connection cable should be plugged into the ANALYZER connector with the blue wires on top (NXP logo side) and the black wires on the bottom.
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The supplied 8-pin connectors cable is fitting the Saleae Logic 8 and Logic Pro 8/16 analyzer series input connectors. To connect to the Saleae Logic Analyzer, the cable should be plugged with the blue wires on top (Saleae logo side) and the black wires on the bottom.
Figure 5. Saleae Logic Analyzer
Saleae provides a software interface with its product to help decode the acquired signals. To learn more, visit the Saleae website.
Plug-ins and extensions for the Saleae Logic Analyzer software are available to decode TPL frames. Visit section 4 for more details.
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The TPL sniffer can be powered through the USB Micro-B connector (J4, labeled PWR) by a 5.0 V source with 50 mA (average) and 150 mA (peak), typically a USB power bank or a USB cable connected to a computer.
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The purpose of the keep-alive feature is to avoid the activation of the automatic shutdown feature found on most consumer USB power banks. Such a shutdown would likely occur due to the limited power consumption of the TPL sniffer circuit alone, in the 10 mA to 20 mA range. Therefore, the sniffer activates an additional 150 mA of internal power consumption with a period of 5.8 seconds and a duty cycle of 20 % (all figures are approximate). This simulates a load large enough to keep most power banks energized.
If the power-on LED indicator goes out shortly after the TPL sniffer is first powered up with a power bank, consider trying another power bank model.
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The TPL Decoder is a high level analyzer (HLA) extension for the Saleae Logic Software. It helps decoding the NXP TPL protocols on several physical layers.
Figure 6. TPL Decoder high level analyzer (HLA)
This tool is also part of the NXP BMS communication decoder ecosystem and can work together with the KIT-TPLSNIFEVB hardware board that facilitates the acquisition of electrical transport protocol link (ETPL) signals.
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The downloadable package contains the TPL Decoder installer along with a release notes and software content register (SCR) files. More information about supported devices and physical layers covered in the latest version can be found the the release notes file.
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The TPL Decoder is a high level analyzer (HLA) extension for the Saleae Logic Software. Therefore the recommended Saleae Logic Software version (see release notes file) must be installed prior to the TPL Decoder installation. Visit the Saleae website to download the Saleae Logic Software.
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Refer to the release notes file for installation steps.
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Guidance on using TPL Decoder can be found directly in the Saleae Logic Software by clicking on the TPL Decoder in the Extensions menu.
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Connect with other engineers and get expert advice on designing with the KIT-TPLSNIFEVB Tool on one of our community sites.
Connecting to the ETPL Bus
Optional ETPL Bus Loading
Power and Data Connections
Connecting to the Logic Analyzer
Interfacing with the Saleae Logic Analyzer
Powering the TPL Sniffer
Power Bank Keep-Alive Function