The New ARM^® Cortex^®-M7

The Arm Cortex-M7 improves processing performance substantially with an upgraded processing pipeline. The enhanced pipeline supports execution of multiple instructions per clock cycle, improving the throughput of the core.

As a Kinetis MCU product marketer, I always look forward to seeing how the wizards of the embedded design community utilize Kinetis MCUs to create game-changing devices. With the newly announced Arm Cortex-M7 core, and its expanded capabilities, I am excited to see what the future will bring for all market segments as more SOCs integrate the new core. There are several attributes of the Cortex-M7 that I believe will imbue end applications: compatibility with the Arm Cortex-M4, and other Cortex-M-class cores, enhanced processing performance, higher performance system busses and cache for internal and external memories. Exploring these aspects of the Cortex-M7 will give insight into the capabilities of this new core.

The compatibility aspects of the Cortex-M7 bring a wide range of pre-built resources to be utilized by embedded creators. Compilers, libraries and even application code will all benefit with an easy migration from previous devices.  This is expected to shorten development times and allow SOCs that integrate the new Cortex-M7 core to be used to generate devices possibly by the end of 2015. Compatibility will allow hours of software work for functions such as voice recognition, sensor fusion or performance optimization of control applications to be directly transferred over to new designs. Embedded designers will find that their time spent finely optimizing application code can be directly ported to new devices with the enhanced Cortex-M-class core. Hence the new performance enhancements of the Cortex-M7 can be utilized with little or no software work.

The Arm Cortex-M7 improves processing performance substantially with an upgraded processing pipeline. The enhanced pipeline supports execution of multiple instructions per clock, improving the throughput of the core.  The higher processing performance can be used to perform functions in a shorter amount of time. Specifically, there are two aspects of the processing performance that will affect end applications – especially those requiring lower power consumption. First, having more capabilities per clock cycle, will allow a task to be completed at lower system clock speeds. Digital filters which previously required 200MHz to operate can now be done at 100MHz. In addition, the computational improvements will allow designs to take advantage of low-power run modes as the improvements can be realized at all CPU speeds. Second, another strategy for low-power design is completing tasks as quickly as possible. Along with the processing throughput, the Arm Cortex-M7 supports higher CPU speeds. So when using the new core to its fullest capabilities, time spent in active modes processing can be reduced, which will allow applications to spend more time in low-power modes.

In order to ensure that the Cortex-M7 core is fed the instructions and data needed to support its upgraded processing, several changes have been made to the system buses of the core. Instruction and data buses have been enlarged to be 64-bit over the previous 32-bit busses, enabling multiple instructions to be fetched per clock cycle. In addition, the high performance 64-bit AXI system bus, is a type of system interconnect that is new for Cortex-M-class cores. It’s built to be optimized for throughput as it supports multiple transactions and queuing of transactions. Attached to the AXI bus are configurable instruction and data caches that provide low latency buffering of information as it is fetched from slower memories. The resulting microarchitecture creates a micro-computer that is much more functional with external memories. The end result is expected to be Cortex-M-class designs with more captivating user interfaces, more data logging capabilities and unlimited firmware space.  As some of these features are optional and dependent on how the SOCs are designed, the benefit will depend greatly on the system architecture for a particular product.

The Kinetis MCU portfolio is well positioned to take full advantage of these thrilling new features, such as the AXI bus and cache, provided by the new Arm Cortex-M7 core. Within the Kinetis K series, there are already Cortex-M4-based devices that include caches and external memory interfaces, such as DRAM that deliver the highest performance benchmarks for Cortex-M-based devices. Kinetis MCU system architects are leveraging these existing designs for new Kinetis products built with the Arm Cortex-M7. To take advantage of the performance benefits, Kinetis devices have key features in regards to power efficiency. Power modes such as high-speed run mode and very low-power run mode dynamically change the power management of Kinetis devices. High-speed run mode will complete tasks as quickly as possible. Very low-power run mode can be used to extract more processing from the Cortex-M7 core at lower CPU speeds.

Finally, you can tap into the broadest portfolio of MCUs built on Arm Cortex-M cores, with close to 1,000 Kinetis devices in market today. For our customers, the sky is the limit for creating astonishing creations using our devices. We look forward to seeing what the future holds with regards to Arm Cortex-M-based designs. What I know for sure, however, is that it’s going to be awesome!