PowerQUICC® III Processor with DDR2, PCI, PCI Express® | NXP Semiconductors

PowerQUICC® III Processor with DDR2, PCI, PCI Express®

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N true 0 PSPMPC8568Een 53 Application Note Application Note t789 36 Application Note Software Application Note Software t783 4 Data Sheet Data Sheet t520 1 Package Information Package Information t790 2 Product Brief Product Brief t532 1 Reference Manual Reference Manual t877 6 Supporting Information Supporting Information t531 2 User Guide User Guide t792 1 en_US en_US en Data Sheet Data Sheet 1 1 1 English Due to feature similarities, this document covers both the MPC8568E and MPC8567E features. 1241646067662723530655 PSP 1.5 MB None None documents None 1241646067662723530655 /docs/en/data-sheet/MPC8568EEC.pdf 1483930 /docs/en/data-sheet/MPC8568EEC.pdf MPC8568EEC documents N 2009-05-06 MPC8568E/MPC8567E PowerQUICC<sup>&#174;</sup> III Integrated Processor Hardware Specifications - Data Sheet /docs/en/data-sheet/MPC8568EEC.pdf /docs/en/data-sheet/MPC8568EEC.pdf Data Sheet N 980000996212993340 2022-12-07 pdf en Oct 25, 2010 980000996212993340 Data Sheet Y N MPC8568E/MPC8567E PowerQUICC<sup>&#174;</sup> III Integrated Processor Hardware Specifications - Data Sheet Reference Manual Reference Manual 6 2 9 English This QEIWRM reference manual defines the functionality of the QUICC Engine<sup>&#174;</sup> block, a versatile RISC-based communication processor. The QUICC Engine block supports multiple external interfaces and protocols independently from the core processor in an integrated processing device. Use this reference manual in conjunction with your device reference manual to implement the QUICC Engine functionality. 1233608188787709580857 PSP 13.4 MB Registration without Disclaimer None documents Extended 1233608188787709580857 /secured/assets/documents/en/reference-manual/QEIWRM.pdf 13369144 /secured/assets/documents/en/reference-manual/QEIWRM.pdf QEIWRM documents Y N 2016-10-31 QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual /webapp/Download?colCode=QEIWRM /secured/assets/documents/en/reference-manual/QEIWRM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en May 3, 2018 500633505221135046 Reference Manual Y N QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual 3 1 English This reference manual describes the resources defined for the Power ISA embedded environment. 1319210247754725815434 PSP 10.4 MB Registration without Disclaimer None documents Extended 1319210247754725815434 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 10448185 /secured/assets/documents/en/reference-manual/EREF_RM.pdf EREF_RM documents Y N 2016-10-31 EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /webapp/Download?colCode=EREF_RM /secured/assets/documents/en/reference-manual/EREF_RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jun 26, 2014 500633505221135046 Reference Manual Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 4 1.2 English E500CORER: This errata document describes corrections to the PowerPC &#8482; e500 Core Family Reference Manual, Revision 1. 1152820363245707387417 PSP 117.9 KB None None documents None 1152820363245707387417 /docs/en/reference-manual/e500CORERMAD.pdf 117856 /docs/en/reference-manual/e500CORERMAD.pdf E500CORERMAD documents N N 2016-10-31 E500CORER, Errata to PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/e500CORERMAD.pdf /docs/en/reference-manual/e500CORERMAD.pdf Reference Manual N 500633505221135046 2022-12-07 pdf N en Sep 11, 2012 500633505221135046 Reference Manual N E500CORER, Errata to PowerPC ™ e500 Core Family - Reference Manual 5 1.2 English This errata describes corrections to the MPC8568E PowerQUICC<sup>&#174;</sup> III\TM Integrated Processor Family Reference Manual, Revision 1. 1213851222026726287806 PSP 543.2 KB None None documents None 1213851222026726287806 /docs/en/reference-manual/MPC8568ERMAD.pdf 543181 /docs/en/reference-manual/MPC8568ERMAD.pdf MPC8568ERMAD documents N 2008-06-19 Errata to MPC8568E PowerQUICC<sup>&#174;</sup> III\TM Integrated Processor Family Reference Manual, Rev. 1 /docs/en/reference-manual/MPC8568ERMAD.pdf /docs/en/reference-manual/MPC8568ERMAD.pdf Reference Manual N 500633505221135046 2022-12-07 pdf en Oct 14, 2009 500633505221135046 Reference Manual Y N Errata to MPC8568E PowerQUICC<sup>&#174;</sup> III\TM Integrated Processor Family Reference Manual, Rev. 1 6 1 English This reference manual defines the functionality of the MPC8568E. This device integrates a processor core based on Power Architecture &#8482; technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The e500v2 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the Power Architecture technology. 1192477849364736022926 PSP 12.8 MB None None documents None 1192477849364736022926 /docs/en/reference-manual/MPC8568ERM.pdf 12765397 /docs/en/reference-manual/MPC8568ERM.pdf MPC8568ERM documents N 2007-10-15 MPC8568E PowerQUICC<sup>&#174;</sup> &#8482; III Integrated Processor Family - Reference Manual /docs/en/reference-manual/MPC8568ERM.pdf /docs/en/reference-manual/MPC8568ERM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf en Jun 6, 2008 500633505221135046 Reference Manual Y N MPC8568E PowerQUICC<sup>&#174;</sup> &#8482; III Integrated Processor Family - Reference Manual 7 1 English The primary objective of this user&#8217;s manual is to describe the functionality of the e500 embedded microprocessor core for software and hardware developers. The e500 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the PowerPC architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words in the 64-bit general-purpose registers (GPRs). 111qmdXB PSP 5.7 MB None None documents None 111qmdXB /docs/en/reference-manual/E500CORERM.pdf 5707515 /docs/en/reference-manual/E500CORERM.pdf E500CORERM documents N 2016-10-31 PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/E500CORERM.pdf /docs/en/reference-manual/E500CORERM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf en May 11, 2005 500633505221135046 Reference Manual N PowerPC ™ e500 Core Family - Reference Manual Application Note Application Note 36 8 2 English Using the Core and System Performance Monitors 1493403864930712885479 PSP 278.3 KB Registration without Disclaimer None documents Extended 1493403864930712885479 /secured/assets/documents/en/application-note/AN3636.pdf 278345 /secured/assets/documents/en/application-note/AN3636.pdf AN3636 documents Y N 2017-04-28 PowerQUICC III Performance Monitors /webapp/Download?colCode=AN3636 /secured/assets/documents/en/application-note/AN3636.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Apr 28, 2017 645036621402383989 Application Note Y N PowerQUICC III Performance Monitors 9 3 English This document is a supplement to the SEC 2/3x reference device driver. 1224778148188710027580 PSP 1.1 MB Registration without Disclaimer None documents Extended 1224778148188710027580 /secured/assets/documents/en/application-note/AN3645.pdf 1147132 /secured/assets/documents/en/application-note/AN3645.pdf AN3645 documents Y N 2016-10-31 SEC 2/3x Descriptor Programmer’s Guide /webapp/Download?colCode=AN3645 /secured/assets/documents/en/application-note/AN3645.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Apr 28, 2017 645036621402383989 Application Note N SEC 2/3x Descriptor Programmer’s Guide 10 11 English AN2583: This application note provides programming guidelines for the PowerQUICC<sup>&#174;</sup> DDR-SDRAM memory controller and specifically JEDEC-compatible DDR1 SDRAM memories. 1070297961506735248621 PSP 333.2 KB None None documents None 1070297961506735248621 /docs/en/application-note/AN2583.pdf 333170 /docs/en/application-note/AN2583.pdf AN2583 documents N N 2003-12-01 AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note /docs/en/application-note/AN2583.pdf /docs/en/application-note/AN2583.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jul 29, 2014 645036621402383989 Application Note Y N AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note 11 2 English This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. 1363012931515701443659 PSP 269.4 KB None None documents None 1363012931515701443659 /docs/en/application-note/AN4531.pdf 269380 /docs/en/application-note/AN4531.pdf AN4531 documents N N 2016-10-31 AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf /docs/en/application-note/AN4531.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Dec 16, 2013 645036621402383989 Application Note N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 12 Rev. 0 English This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. 1305312143395731535528 PSP 577.2 KB Registration without Disclaimer None documents Extended 1305312143395731535528 /secured/assets/documents/en/application-note/AN4311.pdf 577164 /secured/assets/documents/en/application-note/AN4311.pdf AN4311 documents Y N 2016-10-31 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /webapp/Download?colCode=AN4311 /secured/assets/documents/en/application-note/AN4311.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 13, 2011 645036621402383989 Application Note Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 13 0 English AN3830: This application note provides a practical guide to using Our CodeWarrior IDE to debug hardware. Focusing on PowerQUICC<sup>&#174;</sup> processors, this document covers many of the key features available in the IDE to assist in bring-up and troubleshooting of a new board. 1245429781973738421244 PSP 1.6 MB None None documents None 1245429781973738421244 /docs/en/application-note/AN3830.pdf 1576181 /docs/en/application-note/AN3830.pdf AN3830 documents N 2009-06-19 AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes /docs/en/application-note/AN3830.pdf /docs/en/application-note/AN3830.pdf Application Note N 645036621402383989 2022-12-07 pdf en Feb 1, 2011 645036621402383989 Application Note Y N AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes 14 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939 /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors 15 1 English This application note explains the contents of the leader device tree in a multicore Hypervisor implementation used to allocate system resources to the individual partitions.&#13;&#10;Additionally, it describes the contents of the individual device trees that each partition uses for local allocation of those resources. 1225213465876727613770 PSP 828.9 KB None None documents None 1225213465876727613770 /docs/en/application-note/AN3649.pdf 828938 /docs/en/application-note/AN3649.pdf AN3649 documents N N 2016-10-31 Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations /docs/en/application-note/AN3649.pdf /docs/en/application-note/AN3649.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Apr 19, 2010 645036621402383989 Application Note Y N Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations 16 1 English This document assists the user in creating descriptors for requirements not covered in the SEC 2.0 reference device driver. 1107896125362744400814 PSP 765.5 KB None None documents None 1107896125362744400814 /docs/en/application-note/AN2755.pdf 765493 /docs/en/application-note/AN2755.pdf AN2755 documents N 2005-02-08 SEC 2.0 Descriptor Programmer's Guide /docs/en/application-note/AN2755.pdf /docs/en/application-note/AN2755.pdf Application Note N 645036621402383989 2022-12-07 pdf en Apr 7, 2010 645036621402383989 Application Note Y N SEC 2.0 Descriptor Programmer's Guide 17 1 English This application note describes the recommended microcode download procedure on QUICC Engine<sup>&#174;</sup> block-enabled devices, and when and how microcode should be downloaded. 1254777635514719266846 PSP 187.2 KB Registration without Disclaimer None documents Extended 1254777635514719266846 /secured/assets/documents/en/application-note/AN3946.pdf 187225 /secured/assets/documents/en/application-note/AN3946.pdf AN3946 documents Y N 2016-10-31 Downloading Microcode On QUICC Engine™ Block-Enabled Devices /webapp/Download?colCode=AN3946 /secured/assets/documents/en/application-note/AN3946.pdf Application Note N 645036621402383989 2024-11-26 pdf Y en Apr 1, 2010 645036621402383989 Application Note Y N Downloading Microcode On QUICC Engine™ Block-Enabled Devices 18 0 English AN4064: This document explains how to enable and utilize 36-bit physical addressing. It describes the 36-bit capabilities of the e600 and e500v2, and later processor families. Addressing and memory management in a computer system is a difficult topic that is largely beyond the scope of this document. This section explains some of the basic concepts that are essential to understand in order to develop system-level software that utilizes 36-bit physical addressing. 1269842191514722596708 PSP 576.8 KB None None documents None 1269842191514722596708 /docs/en/application-note/AN4064.pdf 576818 /docs/en/application-note/AN4064.pdf AN4064 documents N 2016-10-31 AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes /docs/en/application-note/AN4064.pdf /docs/en/application-note/AN4064.pdf Application Note N 645036621402383989 2022-12-07 pdf en Mar 28, 2010 645036621402383989 Application Note N AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes 19 1 English This application note describes basic jitter terminology and the aspects pertaining to the SYSCLK clock design requirements. 1264143083962735811350 PSP 514.4 KB None None documents None 1264143083962735811350 /docs/en/application-note/AN4056.pdf 514364 /docs/en/application-note/AN4056.pdf AN4056 documents N 2016-10-31 Understanding SYSCLK Jitter /docs/en/application-note/AN4056.pdf /docs/en/application-note/AN4056.pdf Application Note N 645036621402383989 2022-12-07 pdf en Feb 18, 2010 645036621402383989 Application Note N Understanding SYSCLK Jitter 20 0 English AN4026SW.zip /secured/assets/documents/en/application-note-software/AN4026SW.zip /webapp/Download?colCode=AN4026SW&appType=license&docLang=en A common use of the QUICC Engine block is to establish an HDLC communication path over a TDM interface, such as a T1 or E1 link. This application note describes the various sub-blocks used in the QUICC Engine communications engine for this application, discusses how the sub-blocks interoperate with each other, describes how to initialize them for the HDLC communication path, and provides a software demonstration of HDLC mode via a TDM interface using on-chip loopback. 1260992898773711434436 PSP 718.0 KB None None documents None 1260992898773711434436 /docs/en/application-note/AN4026.pdf 718019 /docs/en/application-note/AN4026.pdf AN4026 documents N 2009-12-17 Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC /docs/en/application-note/AN4026.pdf /docs/en/application-note/AN4026.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 17, 2009 645036621402383989 Application Note N Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC 21 0 English High-level data link control (HDLC) is widely used in the telecommunications and networking industries. NXP&#8217;s PowerQUICC&#8482; communications processors have extensive support for HDLC protocol through the communications processor module (CPM) and QUICC Engine&#8482; technologies.&#13;&#10;&#13;&#10;This application note explains how NXP&#8217;s existing&#13;&#10;PowerQUICC communications processors use the CPM and QUICC Engine technologies to support the HDLC protocol and provides HDLC e 1258066893562722616236 PSP 496.6 KB None None documents None 1258066893562722616236 /docs/en/application-note/AN3966.pdf 496625 /docs/en/application-note/AN3966.pdf AN3966 documents N 2016-10-31 PowerQUICC™ HDLC Support and Example Code /docs/en/application-note/AN3966.pdf /docs/en/application-note/AN3966.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 10, 2009 645036621402383989 Application Note N PowerQUICC™ HDLC Support and Example Code 22 2 English NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. 1213738938672737755656 PSP 495.3 KB None None documents None 1213738938672737755656 /docs/en/application-note/AN3638.pdf 495318 /docs/en/application-note/AN3638.pdf AN3638 documents N N 2016-10-31 The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf /docs/en/application-note/AN3638.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Oct 26, 2009 645036621402383989 Application Note N The SystemID Format for Power Architecture™ Development Systems 23 0 English This document is an overview of how to configure&#13;&#10;PowerQUICC<sup>&#174;</sup> III and QorIQ<sup>&#174;</sup> P1xx/P2xx devices to boot from serial RapidIO&#8482; or PCI Express&#8482; with no additional boot flash/EEPROM. 1256145464773713684480 PSP 543.1 KB Registration without Disclaimer None documents Extended 1256145464773713684480 /secured/assets/documents/en/application-note/AN3646.pdf 543108 /secured/assets/documents/en/application-note/AN3646.pdf AN3646 documents Y N 2016-10-31 Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx /webapp/Download?colCode=AN3646 /secured/assets/documents/en/application-note/AN3646.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Oct 21, 2009 645036621402383989 Application Note N Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx 24 2 English AN2810SW.zip /secured/assets/documents/en/application-note-software/AN2810SW.zip /webapp/Download?colCode=AN2810SW&appType=license&docLang=en This application note describes how to effectively program and use the universal programmable machine (UPM) in the PowerQUICC<sup>&#174;</sup> line of communication processors through NXP&#8217;s UPM software tools. 1104253596524716967025 PSP 807.8 KB None None documents None 1104253596524716967025 /docs/en/application-note/AN2810.pdf 807775 /docs/en/application-note/AN2810.pdf AN2810 documents N 2005-01-03 PowerQUICC<sup>&#174;</sup>&#8482; UPM Configuration /docs/en/application-note/AN2810.pdf /docs/en/application-note/AN2810.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 20, 2009 645036621402383989 Application Note Y N PowerQUICC<sup>&#174;</sup>&#8482; UPM Configuration 25 0 English This application note explains how the RFC1990 M&#13;&#10;algorithm can be augmented to detect fragment loss in a way that guarantees an acceptable QoS. It is relevant for NXP Semiconductors&#8217;s MLPPP-enabled, QUICC Engine<sup>&#174;</sup>&#8482; products (MPC8360E, MPC8568E, and MPC8569E). 1255626184525733924891 PSP 498.7 KB None None documents None 1255626184525733924891 /docs/en/application-note/AN3881.pdf 498742 /docs/en/application-note/AN3881.pdf AN3881 documents N 2009-10-19 Ensuring Acceptable QoS by Detecting MLPPP Fragment Loss in Low Density Traffic /docs/en/application-note/AN3881.pdf /docs/en/application-note/AN3881.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 15, 2009 645036621402383989 Application Note Y N Ensuring Acceptable QoS by Detecting MLPPP Fragment Loss in Low Density Traffic 26 0 English This document describes how to configure the QE for extended frame filtering mode using programmable parse command descriptor (PCD). 1255533033120707371907 PSP 664.1 KB None None documents None 1255533033120707371907 /docs/en/application-note/AN3880.pdf 664148 /docs/en/application-note/AN3880.pdf AN3880 documents N 2016-10-31 Ethernet Extended Frame Filtering (PCD) /docs/en/application-note/AN3880.pdf /docs/en/application-note/AN3880.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 14, 2009 645036621402383989 Application Note N Ethernet Extended Frame Filtering (PCD) 27 0 English This application note explains configuration&#13;&#10;requirements to assist users to successfully program and set up this interface type. It also compares SGMII to other gigabit Ethernet standards and interfaces. 1244236817778728476903 PSP 692.4 KB Registration without Disclaimer None documents Extended 1244236817778728476903 /secured/assets/documents/en/application-note/AN3869.pdf 692438 /secured/assets/documents/en/application-note/AN3869.pdf AN3869 documents Y N 2016-10-31 Implementing SGMII Interfaces on the PowerQUICC™ III /webapp/Download?colCode=AN3869 /secured/assets/documents/en/application-note/AN3869.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 5, 2009 645036621402383989 Application Note N Implementing SGMII Interfaces on the PowerQUICC™ III 28 0 English This application note explains the procedures to utilize the extra FC (Flow Control) credits for PCI Express inbound posted memory write transactions, which is currently a hidden feature for the Power QUICC III&#8482; devices. 1243968993550696784184 PSP 476.0 KB None None documents None 1243968993550696784184 /docs/en/application-note/AN3781.pdf 476033 /docs/en/application-note/AN3781.pdf AN3781 documents N 2010-05-11 Utilizing Extra FC Credits for PCI Express Inbound Posted Memory Write Transactions in PowerQUICC III&#8482; Devices /docs/en/application-note/AN3781.pdf /docs/en/application-note/AN3781.pdf Application Note N 645036621402383989 2022-12-07 pdf en Jun 2, 2009 645036621402383989 Application Note N Utilizing Extra FC Credits for PCI Express Inbound Posted Memory Write Transactions in PowerQUICC III&#8482; Devices 29 5 English This document explains how the frequency divider to calculate the SCL speed of the I2C interface is determined for the MPC824x, MPC83xx, MPC85xx, and MPC86xx devices. 1119553728324723212395 PSP 611.4 KB Registration without Disclaimer None documents Extended 1119553728324723212395 /secured/assets/documents/en/application-note/AN2919.pdf 611358 /secured/assets/documents/en/application-note/AN2919.pdf AN2919 documents Y N 2016-10-31 Determining the I2C Frequency Divider Ratio for SCL /webapp/Download?colCode=AN2919 /secured/assets/documents/en/application-note/AN2919.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Dec 31, 2008 645036621402383989 Application Note N Determining the I2C Frequency Divider Ratio for SCL 30 1 English This application note describes the general recommendation for new designs based on the NXP Semiconductors MPC8568E processor family. It may also serve as a useful guide to debug a newly designed system by highlighting those areas of a design that merit special attention during initial system startup. 1201705980181733776295 PSP 562.2 KB None None documents None 1201705980181733776295 /docs/en/application-note/AN3548.pdf 562218 /docs/en/application-note/AN3548.pdf AN3548 documents N 2008-01-30 MPC8568E Design Checklist /docs/en/application-note/AN3548.pdf /docs/en/application-note/AN3548.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 2, 2008 645036621402383989 Application Note Y N MPC8568E Design Checklist 31 1.0 English This application note describes an example of how to use an external DMA engine with a Serial RapidIO&#174; interface. 1208458263255715391554 PSP 505.7 KB None None documents None 1208458263255715391554 /docs/en/application-note/AN3550.pdf 505720 /docs/en/application-note/AN3550.pdf AN3550 documents N 2016-10-31 Using an External DMA Controller with Freescale Processors that Support Serial RapidIO® Technology /docs/en/application-note/AN3550.pdf /docs/en/application-note/AN3550.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 22, 2008 645036621402383989 Application Note N Using an External DMA Controller with Freescale Processors that Support Serial RapidIO® Technology 32 0 English This application note provides an overview and specific strategies for cache coherency and potential performance impacts in the PowerQUICC<sup>&#174;</sup> II Pro and PowerQUICC III families. It focuses on data coherency and potential system issues, as well as some concerns associated with having multiple DMA devices. It also discusses the specific steps and interdependencies required to implement hardware enforced cache coherency. 1198270786976715604383 PSP 547.7 KB None None documents None 1198270786976715604383 /docs/en/application-note/AN3544.pdf 547694 /docs/en/application-note/AN3544.pdf AN3544 documents N 2016-10-31 PowerQUICC™ Data Cache Coherency /docs/en/application-note/AN3544.pdf /docs/en/application-note/AN3544.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 21, 2007 645036621402383989 Application Note N PowerQUICC™ Data Cache Coherency 33 1 English This document describes aspects of memory synchronization and cache coherency requirements for NXP&#8217;s PowerQUICC<sup>&#174;</sup>&#8482; III product family. Coherency and synchronization need be considered, both for data and instructions, when initializing memory or moving memory contents from one location to another. 1191253168152709402147 PSP 189.0 KB None None documents None 1191253168152709402147 /docs/en/application-note/AN3441.pdf 188954 /docs/en/application-note/AN3441.pdf AN3441 documents N 2016-10-31 Coherency and Synchronization Requirements for PowerQUICC™ III /docs/en/application-note/AN3441.pdf /docs/en/application-note/AN3441.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 17, 2007 645036621402383989 Application Note N Coherency and Synchronization Requirements for PowerQUICC™ III 34 0 English This application note provides an introduction to the error correcting code (ECC) technology as well as an aid to initialization and error recovery on Our PowerQUICC<sup>&#174;</sup> III family of processors. 1196228463425717224884 PSP 573.0 KB None None documents None 1196228463425717224884 /docs/en/application-note/AN3532.pdf 572952 /docs/en/application-note/AN3532.pdf AN3532 documents N 2016-10-31 Error Correction and Error Handling on PowerQUICC (TM) III Processors /docs/en/application-note/AN3532.pdf /docs/en/application-note/AN3532.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 27, 2007 645036621402383989 Application Note N Error Correction and Error Handling on PowerQUICC (TM) III Processors 35 1 English This application note explains how the QUICC Engine<sup>&#174;</sup>&#8482; multichannel controller (MCC) and serial interface (SI) of the MPC8360E and MPC8568E can be configured to control 16 E1 or T1 interfaces. 1194627746614711196965 PSP 538.3 KB None None documents None 1194627746614711196965 /docs/en/application-note/AN3536.pdf 538307 /docs/en/application-note/AN3536.pdf AN3536 documents N 2007-11-26 Enhanced Serial Interface Mapping: 16 E1/T1 QUICC Engine<sup>&#174;</sup>&#8482; Solution for TDM Connectivity /docs/en/application-note/AN3536.pdf /docs/en/application-note/AN3536.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 9, 2007 645036621402383989 Application Note Y N Enhanced Serial Interface Mapping: 16 E1/T1 QUICC Engine<sup>&#174;</sup>&#8482; Solution for TDM Connectivity 36 0 English AN3445: This application note outlines general, high-level, architectural differences between the e300 and e500 family processors. The e300 family (which are based on the original 603 design) was designed to the original PowerPC architecture definition. The e500v1 and e500v2 processors are designed to what was originally the PowerPC Book E architecture and NXP?s embedded implementation standards (EIS). 1194389310604697206738 PSP 935.0 KB None None documents None 1194389310604697206738 /docs/en/application-note/AN3445.pdf 934951 /docs/en/application-note/AN3445.pdf AN3445 documents N 2016-10-31 AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3445.pdf /docs/en/application-note/AN3445.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 31, 2007 645036621402383989 Application Note N AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes 37 0 English AN3531: This application note outlines general, high-level, architectural differences between the e600 and e500 family processors. Is intended as a general guideline for programmers and system designers who are assessing the efforts required in migrating to e500-based devices. 1194389312415718217914 PSP 961.6 KB None None documents None 1194389312415718217914 /docs/en/application-note/AN3531.pdf 961596 /docs/en/application-note/AN3531.pdf AN3531 documents N N 2016-10-31 AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3531.pdf /docs/en/application-note/AN3531.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Oct 31, 2007 645036621402383989 Application Note N AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes 38 2 English These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. 1128961595061725581551 PSP 619.7 KB None None documents None 1128961595061725581551 /docs/en/application-note/AN2910.pdf 619650 /docs/en/application-note/AN2910.pdf AN2910 documents N 2016-10-31 Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf /docs/en/application-note/AN2910.pdf Application Note N 645036621402383989 2022-12-07 pdf en Mar 27, 2007 645036621402383989 Application Note N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces 39 0 English This document reviews the use of Ethernet and RapidIO as a system interconnect fabric, comparing them against the requirements for such fabrics. Quantitative analysis is presented where possible. 1171553356793694633748 PSP 784.2 KB None None documents None 1171553356793694633748 /docs/en/application-note/AN3088.pdf 784203 /docs/en/application-note/AN3088.pdf AN3088 documents N 2007-02-15 System Interconnect Fabrics: Ethernet Versus RapidIO /docs/en/application-note/AN3088.pdf /docs/en/application-note/AN3088.pdf Application Note N 645036621402383989 2022-12-07 pdf en Feb 15, 2007 645036621402383989 Application Note Y N System Interconnect Fabrics: Ethernet Versus RapidIO 40 1 English The architecture for the PowerPC&#8482; instruction set provides two types of synchronizing instructions:&#13;&#10;* Context-synchronizing&#13;&#10;* Execution-synchronizing &#13;&#10;This application note presents a high-level definition and description of each type of synchronizing instruction. 1057245101474727053067 PSP 451.7 KB None None documents None 1057245101474727053067 /docs/en/application-note/AN2540.pdf 451663 /docs/en/application-note/AN2540.pdf AN2540 documents N 2003-07-03 Synchronizing Instructions for PowerPC(TM) Instruction Set Architecture /docs/en/application-note/AN2540.pdf /docs/en/application-note/AN2540.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 8, 2006 645036621402383989 Application Note Y N Synchronizing Instructions for PowerPC(TM) Instruction Set Architecture 41 0 English This document provides guidelines for basic use of the PowerQUICC<sup>&#174;</sup> III serial RapidIO interface. 1133538491299733535557 PSP 1.1 MB None None documents None 1133538491299733535557 /docs/en/application-note/AN2932.pdf 1052512 /docs/en/application-note/AN2932.pdf AN2932 documents N 2005-12-02 Serial RapidIO Bring-Up Procedure on PowerQUICC<sup>&#174;</sup> III /docs/en/application-note/AN2932.pdf /docs/en/application-note/AN2932.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 2, 2005 645036621402383989 Application Note Y N Serial RapidIO Bring-Up Procedure on PowerQUICC<sup>&#174;</sup> III 42 0 English This application note is provided to assist those engineers wishing to use the serial RapidIO message unit on the PowerQUICC<sup>&#174;</sup>&#8482; III. It summarizes the features and uses of the RapidIO messaging unit (including data messages, doorbell messages and inbound port-writes) and provides example code. These extracted code segments are part of a simple application, written to run on top of U-Boot, to prove the functionality of the messaging unit. 1127154752940725970276 PSP 530.6 KB None None documents None 1127154752940725970276 /docs/en/application-note/AN2923.pdf 530575 /docs/en/application-note/AN2923.pdf AN2923 documents N 2005-09-19 Using the Serial RapidIO Messaging Unit on PowerQUICC<sup>&#174;</sup> III /docs/en/application-note/AN2923.pdf /docs/en/application-note/AN2923.pdf Application Note N 645036621402383989 2022-12-07 pdf en Sep 19, 2005 645036621402383989 Application Note Y N Using the Serial RapidIO Messaging Unit on PowerQUICC<sup>&#174;</sup> III 43 0 English Simplified Mnemonics for PowerPC Instructions. 1064950886097724682016 PSP 1.4 MB None None documents None 1064950886097724682016 /docs/en/application-note/AN2491.pdf 1379878 /docs/en/application-note/AN2491.pdf AN2491 documents N 2003-09-30 Simplified Mnemonics for PowerPC Instructions /docs/en/application-note/AN2491.pdf /docs/en/application-note/AN2491.pdf Application Note N 645036621402383989 2022-12-07 pdf en Sep 30, 2003 645036621402383989 Application Note Y N Simplified Mnemonics for PowerPC Instructions User Guide User Guide 1 44 0 English This document explains how to use each component of the MPC8568E-MDS-PB modular&#13;&#10;development kit. 1204820320338725985861 PSP 1.2 MB None None documents None 1204820320338725985861 /docs/en/user-guide/MPC8568EMDSPBKCG.pdf 1201512 /docs/en/user-guide/MPC8568EMDSPBKCG.pdf MPC8568EMDSPBKCG documents N 2008-03-06 MPC8568E Development Kit Kit Configuration Guide /docs/en/user-guide/MPC8568EMDSPBKCG.pdf /docs/en/user-guide/MPC8568EMDSPBKCG.pdf User Guide N 132339537837198660 2023-06-18 pdf en Feb 29, 2008 132339537837198660 User Guide Y N MPC8568E Development Kit Kit Configuration Guide Application Note Software Application Note Software 4 45 1 English This is a software demonstration of HDLC mode via a TDM interface using on-chip loopback. The demonstration software in this application note were developed and verified using the MPC8360E&#13;&#10;device in a MPC8360E-RDK system. This note applies to any MPC83xx or MPC85xx device with a QUICC Engine<sup>&#174;</sup> block, although small differences in device and system configuration will require minor changes to the software. 1261066595823727647254 PSP 26.7 KB Registration With Click-Thru Software Licensing Agreement 1395958162559706127527 documents Extended 1261066595823727647254 /secured/assets/documents/en/application-note-software/AN4026SW.zip 26724 /secured/assets/documents/en/application-note-software/AN4026SW.zip AN4026SW documents Y N 2016-10-31 Software to accompany application note AN4026. /webapp/Download?colCode=AN4026SW&appType=license /secured/assets/documents/en/application-note-software/AN4026SW.zip Application Note Software N 789425793691620447 2022-12-07 zip Y en Dec 18, 2009 789425793691620447 Application Note Software N Software to accompany application note AN4026. 46 0 English 1258066894053701788655 PSP 330.9 KB Registration With Click-Thru Software Licensing Agreement 1395958162559706127527 documents Extended 1258066894053701788655 /secured/assets/documents/en/application-note-software/AN3966SW.zip 330857 /secured/assets/documents/en/application-note-software/AN3966SW.zip AN3966SW documents Y N 2016-10-31 Software to accompany application note AN3966 /webapp/Download?colCode=AN3966SW&appType=license /secured/assets/documents/en/application-note-software/AN3966SW.zip Application Note Software N 789425793691620447 2022-12-07 zip Y en Nov 10, 2009 789425793691620447 Application Note Software N Software to accompany application note AN3966 47 0 English This application note addresses a common challenge encountered during circuit board testing with some of the newer NXP microprocessors. It is common practice for board testing houses to test for shorts on the power rails by measuring the resistance from a power rail to the ground rail. In older technologies, this is a reasonable approach. However, this application note explains why this approach can be problematic when used with devices in newer technologies. 1181767584945705509512 PSP 163.7 KB None None documents None 1181767584945705509512 /docs/en/application-note-software/AN3372.pdf 163681 /docs/en/application-note-software/AN3372.pdf AN3372 documents N 2016-10-31 Challenges in Testing for Power Rail Shorts with New Technologies /docs/en/application-note-software/AN3372.pdf /docs/en/application-note-software/AN3372.pdf Application Note Software N 789425793691620447 2022-12-07 pdf en Jun 13, 2007 789425793691620447 Application Note Software N Challenges in Testing for Power Rail Shorts with New Technologies 48 2 English AN2810, PowerQUICC<sup>&#174;</sup> UPM Configuration, PowerQUICC, Universal Programmable Machine, Configuration, Application Note 1113503860374718430905 PSP 5.6 KB Registration With Click-Thru Software Licensing Agreement 1395958162559706127527 documents Extended 1113503860374718430905 /secured/assets/documents/en/application-note-software/AN2810SW.zip 5555 /secured/assets/documents/en/application-note-software/AN2810SW.zip AN2810SW documents Y N 2005-04-14 AN2810 Supporting Files /webapp/Download?colCode=AN2810SW&appType=license /secured/assets/documents/en/application-note-software/AN2810SW.zip Application Note Software N 789425793691620447 2022-12-07 zip Y en Aug 15, 2006 789425793691620447 Application Note Software N AN2810 Supporting Files Package Information Package Information 2 49 1 English This document is a presentation on understanding the FC-PBGA package. 1273780789511716723050 PSP 5.2 MB None None documents None 1273780789511716723050 /docs/en/package-information/FC-PBGAPRES.pdf 5219387 /docs/en/package-information/FC-PBGAPRES.pdf FC-PBGAPRES documents N N 2016-10-31 Flip Chip Plastic Ball Grid Array (FC-PBGA) Presentation /docs/en/package-information/FC-PBGAPRES.pdf /docs/en/package-information/FC-PBGAPRES.pdf Package Information N 302435339416912908 2022-12-07 pdf N en Jul 8, 2015 302435339416912908 Package Information N Flip Chip Plastic Ball Grid Array (FC-PBGA) Presentation 50 0 English 1208190321586716421830 PSP 2.0 KB None None documents None 1208190321586716421830 /docs/en/package-information/MPC8568FLOTHERM.zip 2036 /docs/en/package-information/MPC8568FLOTHERM.zip MPC8568FLOTHERM documents N N 2016-10-31 MPC8568E PowerQUICC™ III Thermal Simulation Report and Models /docs/en/package-information/MPC8568FLOTHERM.zip /docs/en/package-information/MPC8568FLOTHERM.zip Package Information N 302435339416912908 2022-12-07 zip N en Apr 13, 2008 302435339416912908 Package Information Y N MPC8568E PowerQUICC™ III Thermal Simulation Report and Models Product Brief Product Brief 1 51 0 English This document provides an overview of features and functionality of the MPC8568E PowerQUICC<sup>&#174;</sup> III &#8482; integrated communications processor. The MPC8568E offers an excellent combination of protocol and interface support including interworking, a high performance PowerPC CPU with a large L2 cache, a DDR memory controller, and high-speed interfaces such as serial RapidIO and PCI Express. 1160508756184714843480 PSP 572.9 KB None None documents None 1160508756184714843480 /docs/en/product-brief/MPC8568EPB.pdf 572903 /docs/en/product-brief/MPC8568EPB.pdf MPC8568EPB documents N 2006-10-10 MPC8568E Integrated Processor - Product Brief /docs/en/product-brief/MPC8568EPB.pdf /docs/en/product-brief/MPC8568EPB.pdf Product Brief N 899114358132306053 2022-12-07 pdf en Sep 29, 2006 899114358132306053 Product Brief Y N MPC8568E Integrated Processor - Product Brief Supporting Information Supporting Information 2 52 1.9 English FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. 1368836090577704535160 PSP 303.5 KB None None documents None 1368836090577704535160 /docs/en/supporting-information/FSLNISTCAVP.pdf 303546 /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP documents N N 2016-11-09 FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf /docs/en/supporting-information/FSLNISTCAVP.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 28, 2016 371282830530968666 Supporting Information Y N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 53 2 English Customer Export Control Information Document 1232680176147728092093 PSP 215.2 KB None None documents None 1232680176147728092093 /docs/en/supporting-information/MPC8568EFAMPECI.pdf 215247 /docs/en/supporting-information/MPC8568EFAMPECI.pdf MPC8568EFAMPECI documents N N 2016-10-31 MPC8568 Family Customer Export Control Information /docs/en/supporting-information/MPC8568EFAMPECI.pdf /docs/en/supporting-information/MPC8568EFAMPECI.pdf Supporting Information N 371282830530968666 2023-06-19 pdf N en Dec 10, 2010 371282830530968666 Supporting Information Y N MPC8568 Family Customer Export Control Information false 0 MPC8568E downloads en true 1 Y PSP Application Note 36 /secured/assets/documents/en/application-note/AN3636.pdf 2017-04-28 1493403864930712885479 PSP 8 Apr 28, 2017 Application Note Using the Core and System Performance Monitors Registration without Disclaimer /secured/assets/documents/en/application-note/AN3636.pdf English documents 278345 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3636 PowerQUICC III Performance Monitors /secured/assets/documents/en/application-note/AN3636.pdf documents 645036621402383989 Application Note N en Extended Y pdf 2 Y N PowerQUICC III Performance Monitors 278.3 KB AN3636 N 1493403864930712885479 /secured/assets/documents/en/application-note/AN3645.pdf 2016-10-31 1224778148188710027580 PSP 9 Apr 28, 2017 Application Note This document is a supplement to the SEC 2/3x reference device driver. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3645.pdf English documents 1147132 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3645 SEC 2/3x Descriptor Programmer’s Guide /secured/assets/documents/en/application-note/AN3645.pdf documents 645036621402383989 Application Note N en Extended pdf 3 Y N SEC 2/3x Descriptor Programmer’s Guide 1.1 MB AN3645 N 1224778148188710027580 /docs/en/application-note/AN2583.pdf 2003-12-01 1070297961506735248621 PSP 10 Jul 29, 2014 Application Note AN2583: This application note provides programming guidelines for the PowerQUICC<sup>&#174;</sup> DDR-SDRAM memory controller and specifically JEDEC-compatible DDR1 SDRAM memories. None /docs/en/application-note/AN2583.pdf English documents 333170 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN2583.pdf AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note /docs/en/application-note/AN2583.pdf documents 645036621402383989 Application Note N en None Y pdf 11 N N AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note 333.2 KB AN2583 N 1070297961506735248621 /docs/en/application-note/AN4531.pdf 2016-10-31 1363012931515701443659 PSP 11 Dec 16, 2013 Application Note This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. None /docs/en/application-note/AN4531.pdf English documents 269380 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4531.pdf AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf documents 645036621402383989 Application Note N en None pdf 2 N N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 269.4 KB AN4531 N 1363012931515701443659 /secured/assets/documents/en/application-note/AN4311.pdf 2016-10-31 1305312143395731535528 PSP 12 May 13, 2011 Application Note This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4311.pdf English documents 577164 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4311 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /secured/assets/documents/en/application-note/AN4311.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev. 0 Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 577.2 KB AN4311 N 1305312143395731535528 /docs/en/application-note/AN3830.pdf 2009-06-19 1245429781973738421244 PSP 13 Feb 1, 2011 Application Note AN3830: This application note provides a practical guide to using Our CodeWarrior IDE to debug hardware. Focusing on PowerQUICC<sup>&#174;</sup> processors, this document covers many of the key features available in the IDE to assist in bring-up and troubleshooting of a new board. None /docs/en/application-note/AN3830.pdf English documents 1576181 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3830.pdf AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes /docs/en/application-note/AN3830.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N AN3830, Hardware Debugging Using the CodeWarrior<sup>&#174;</sup> &#8482; IDE - Application Notes 1.6 MB AN3830 N 1245429781973738421244 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 14 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939 DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 /docs/en/application-note/AN3649.pdf 2016-10-31 1225213465876727613770 PSP 15 Apr 19, 2010 Application Note This application note explains the contents of the leader device tree in a multicore Hypervisor implementation used to allocate system resources to the individual partitions.&#13;&#10;Additionally, it describes the contents of the individual device trees that each partition uses for local allocation of those resources. None /docs/en/application-note/AN3649.pdf English documents 828938 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3649.pdf Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations /docs/en/application-note/AN3649.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations 828.9 KB AN3649 N 1225213465876727613770 /docs/en/application-note/AN2755.pdf 2005-02-08 1107896125362744400814 PSP 16 Apr 7, 2010 Application Note This document assists the user in creating descriptors for requirements not covered in the SEC 2.0 reference device driver. None /docs/en/application-note/AN2755.pdf English documents 765493 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2755.pdf SEC 2.0 Descriptor Programmer's Guide /docs/en/application-note/AN2755.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N SEC 2.0 Descriptor Programmer's Guide 765.5 KB AN2755 N 1107896125362744400814 /secured/assets/documents/en/application-note/AN3946.pdf 2016-10-31 1254777635514719266846 PSP 17 Apr 1, 2010 Application Note This application note describes the recommended microcode download procedure on QUICC Engine<sup>&#174;</sup> block-enabled devices, and when and how microcode should be downloaded. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3946.pdf English documents 187225 None 645036621402383989 2024-11-26 Y /webapp/Download?colCode=AN3946 Downloading Microcode On QUICC Engine™ Block-Enabled Devices /secured/assets/documents/en/application-note/AN3946.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N Downloading Microcode On QUICC Engine™ Block-Enabled Devices 187.2 KB AN3946 N 1254777635514719266846 /docs/en/application-note/AN4064.pdf 2016-10-31 1269842191514722596708 PSP 18 Mar 28, 2010 Application Note AN4064: This document explains how to enable and utilize 36-bit physical addressing. It describes the 36-bit capabilities of the e600 and e500v2, and later processor families. Addressing and memory management in a computer system is a difficult topic that is largely beyond the scope of this document. This section explains some of the basic concepts that are essential to understand in order to develop system-level software that utilizes 36-bit physical addressing. None /docs/en/application-note/AN4064.pdf English documents 576818 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4064.pdf AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes /docs/en/application-note/AN4064.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes 576.8 KB AN4064 N 1269842191514722596708 /docs/en/application-note/AN4056.pdf 2016-10-31 1264143083962735811350 PSP 19 Feb 18, 2010 Application Note This application note describes basic jitter terminology and the aspects pertaining to the SYSCLK clock design requirements. None /docs/en/application-note/AN4056.pdf English documents 514364 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4056.pdf Understanding SYSCLK Jitter /docs/en/application-note/AN4056.pdf documents 645036621402383989 Application Note N en None pdf 1 N Understanding SYSCLK Jitter 514.4 KB AN4056 N 1264143083962735811350 /docs/en/application-note/AN4026.pdf 2009-12-17 1260992898773711434436 PSP 20 Dec 17, 2009 Application Note A common use of the QUICC Engine block is to establish an HDLC communication path over a TDM interface, such as a T1 or E1 link. This application note describes the various sub-blocks used in the QUICC Engine communications engine for this application, discusses how the sub-blocks interoperate with each other, describes how to initialize them for the HDLC communication path, and provides a software demonstration of HDLC mode via a TDM interface using on-chip loopback. None /docs/en/application-note/AN4026.pdf English documents 718019 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4026.pdf Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC /docs/en/application-note/AN4026.pdf documents 645036621402383989 Application Note N en None pdf 0 N Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC 718.0 KB AN4026 N 1260992898773711434436 /docs/en/application-note/AN3966.pdf 2016-10-31 1258066893562722616236 PSP 21 Nov 10, 2009 Application Note High-level data link control (HDLC) is widely used in the telecommunications and networking industries. NXP&#8217;s PowerQUICC&#8482; communications processors have extensive support for HDLC protocol through the communications processor module (CPM) and QUICC Engine&#8482; technologies.&#13;&#10;&#13;&#10;This application note explains how NXP&#8217;s existing&#13;&#10;PowerQUICC communications processors use the CPM and QUICC Engine technologies to support the HDLC protocol and provides HDLC e None /docs/en/application-note/AN3966.pdf English documents 496625 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3966.pdf PowerQUICC™ HDLC Support and Example Code /docs/en/application-note/AN3966.pdf documents 645036621402383989 Application Note N en None pdf 0 N PowerQUICC™ HDLC Support and Example Code 496.6 KB AN3966 N 1258066893562722616236 /docs/en/application-note/AN3638.pdf 2016-10-31 1213738938672737755656 PSP 22 Oct 26, 2009 Application Note NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. None /docs/en/application-note/AN3638.pdf English documents 495318 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3638.pdf The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf documents 645036621402383989 Application Note N en None pdf 2 N N The SystemID Format for Power Architecture™ Development Systems 495.3 KB AN3638 N 1213738938672737755656 /secured/assets/documents/en/application-note/AN3646.pdf 2016-10-31 1256145464773713684480 PSP 23 Oct 21, 2009 Application Note This document is an overview of how to configure&#13;&#10;PowerQUICC<sup>&#174;</sup> III and QorIQ<sup>&#174;</sup> P1xx/P2xx devices to boot from serial RapidIO&#8482; or PCI Express&#8482; with no additional boot flash/EEPROM. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3646.pdf English documents 543108 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3646 Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx /secured/assets/documents/en/application-note/AN3646.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx 543.1 KB AN3646 N 1256145464773713684480 /docs/en/application-note/AN2810.pdf 2005-01-03 1104253596524716967025 PSP 24 Oct 20, 2009 Application Note This application note describes how to effectively program and use the universal programmable machine (UPM) in the PowerQUICC<sup>&#174;</sup> line of communication processors through NXP&#8217;s UPM software tools. None /docs/en/application-note/AN2810.pdf English documents 807775 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2810.pdf PowerQUICC<sup>&#174;</sup>&#8482; UPM Configuration /docs/en/application-note/AN2810.pdf documents 645036621402383989 Application Note N en None Y pdf 2 N PowerQUICC<sup>&#174;</sup>&#8482; UPM Configuration 807.8 KB AN2810 N 1104253596524716967025 /docs/en/application-note/AN3881.pdf 2009-10-19 1255626184525733924891 PSP 25 Oct 15, 2009 Application Note This application note explains how the RFC1990 M&#13;&#10;algorithm can be augmented to detect fragment loss in a way that guarantees an acceptable QoS. It is relevant for NXP Semiconductors&#8217;s MLPPP-enabled, QUICC Engine<sup>&#174;</sup>&#8482; products (MPC8360E, MPC8568E, and MPC8569E). None /docs/en/application-note/AN3881.pdf English documents 498742 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3881.pdf Ensuring Acceptable QoS by Detecting MLPPP Fragment Loss in Low Density Traffic /docs/en/application-note/AN3881.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N Ensuring Acceptable QoS by Detecting MLPPP Fragment Loss in Low Density Traffic 498.7 KB AN3881 N 1255626184525733924891 /docs/en/application-note/AN3880.pdf 2016-10-31 1255533033120707371907 PSP 26 Oct 14, 2009 Application Note This document describes how to configure the QE for extended frame filtering mode using programmable parse command descriptor (PCD). None /docs/en/application-note/AN3880.pdf English documents 664148 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3880.pdf Ethernet Extended Frame Filtering (PCD) /docs/en/application-note/AN3880.pdf documents 645036621402383989 Application Note N en None pdf 0 N Ethernet Extended Frame Filtering (PCD) 664.1 KB AN3880 N 1255533033120707371907 /secured/assets/documents/en/application-note/AN3869.pdf 2016-10-31 1244236817778728476903 PSP 27 Jun 5, 2009 Application Note This application note explains configuration&#13;&#10;requirements to assist users to successfully program and set up this interface type. It also compares SGMII to other gigabit Ethernet standards and interfaces. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3869.pdf English documents 692438 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3869 Implementing SGMII Interfaces on the PowerQUICC™ III /secured/assets/documents/en/application-note/AN3869.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N Implementing SGMII Interfaces on the PowerQUICC™ III 692.4 KB AN3869 N 1244236817778728476903 /docs/en/application-note/AN3781.pdf 2010-05-11 1243968993550696784184 PSP 28 Jun 2, 2009 Application Note This application note explains the procedures to utilize the extra FC (Flow Control) credits for PCI Express inbound posted memory write transactions, which is currently a hidden feature for the Power QUICC III&#8482; devices. None /docs/en/application-note/AN3781.pdf English documents 476033 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3781.pdf Utilizing Extra FC Credits for PCI Express Inbound Posted Memory Write Transactions in PowerQUICC III&#8482; Devices /docs/en/application-note/AN3781.pdf documents 645036621402383989 Application Note N en None pdf 0 N Utilizing Extra FC Credits for PCI Express Inbound Posted Memory Write Transactions in PowerQUICC III&#8482; Devices 476.0 KB AN3781 N 1243968993550696784184 /secured/assets/documents/en/application-note/AN2919.pdf 2016-10-31 1119553728324723212395 PSP 29 Dec 31, 2008 Application Note This document explains how the frequency divider to calculate the SCL speed of the I2C interface is determined for the MPC824x, MPC83xx, MPC85xx, and MPC86xx devices. Registration without Disclaimer /secured/assets/documents/en/application-note/AN2919.pdf English documents 611358 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN2919 Determining the I2C Frequency Divider Ratio for SCL /secured/assets/documents/en/application-note/AN2919.pdf documents 645036621402383989 Application Note N en Extended pdf 5 Y N Determining the I2C Frequency Divider Ratio for SCL 611.4 KB AN2919 N 1119553728324723212395 /docs/en/application-note/AN3548.pdf 2008-01-30 1201705980181733776295 PSP 30 Dec 2, 2008 Application Note This application note describes the general recommendation for new designs based on the NXP Semiconductors MPC8568E processor family. It may also serve as a useful guide to debug a newly designed system by highlighting those areas of a design that merit special attention during initial system startup. None /docs/en/application-note/AN3548.pdf English documents 562218 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3548.pdf MPC8568E Design Checklist /docs/en/application-note/AN3548.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N MPC8568E Design Checklist 562.2 KB AN3548 N 1201705980181733776295 /docs/en/application-note/AN3550.pdf 2016-10-31 1208458263255715391554 PSP 31 Oct 22, 2008 Application Note This application note describes an example of how to use an external DMA engine with a Serial RapidIO&#174; interface. None /docs/en/application-note/AN3550.pdf English documents 505720 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3550.pdf Using an External DMA Controller with Freescale Processors that Support Serial RapidIO® Technology /docs/en/application-note/AN3550.pdf documents 645036621402383989 Application Note N en None pdf 1.0 N Using an External DMA Controller with Freescale Processors that Support Serial RapidIO® Technology 505.7 KB AN3550 N 1208458263255715391554 /docs/en/application-note/AN3544.pdf 2016-10-31 1198270786976715604383 PSP 32 Dec 21, 2007 Application Note This application note provides an overview and specific strategies for cache coherency and potential performance impacts in the PowerQUICC<sup>&#174;</sup> II Pro and PowerQUICC III families. It focuses on data coherency and potential system issues, as well as some concerns associated with having multiple DMA devices. It also discusses the specific steps and interdependencies required to implement hardware enforced cache coherency. None /docs/en/application-note/AN3544.pdf English documents 547694 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3544.pdf PowerQUICC™ Data Cache Coherency /docs/en/application-note/AN3544.pdf documents 645036621402383989 Application Note N en None pdf 0 N PowerQUICC™ Data Cache Coherency 547.7 KB AN3544 N 1198270786976715604383 /docs/en/application-note/AN3441.pdf 2016-10-31 1191253168152709402147 PSP 33 Dec 17, 2007 Application Note This document describes aspects of memory synchronization and cache coherency requirements for NXP&#8217;s PowerQUICC<sup>&#174;</sup>&#8482; III product family. Coherency and synchronization need be considered, both for data and instructions, when initializing memory or moving memory contents from one location to another. None /docs/en/application-note/AN3441.pdf English documents 188954 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3441.pdf Coherency and Synchronization Requirements for PowerQUICC™ III /docs/en/application-note/AN3441.pdf documents 645036621402383989 Application Note N en None pdf 1 N Coherency and Synchronization Requirements for PowerQUICC™ III 189.0 KB AN3441 N 1191253168152709402147 /docs/en/application-note/AN3532.pdf 2016-10-31 1196228463425717224884 PSP 34 Nov 27, 2007 Application Note This application note provides an introduction to the error correcting code (ECC) technology as well as an aid to initialization and error recovery on Our PowerQUICC<sup>&#174;</sup> III family of processors. None /docs/en/application-note/AN3532.pdf English documents 572952 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3532.pdf Error Correction and Error Handling on PowerQUICC (TM) III Processors /docs/en/application-note/AN3532.pdf documents 645036621402383989 Application Note N en None pdf 0 N Error Correction and Error Handling on PowerQUICC (TM) III Processors 573.0 KB AN3532 N 1196228463425717224884 /docs/en/application-note/AN3536.pdf 2007-11-26 1194627746614711196965 PSP 35 Nov 9, 2007 Application Note This application note explains how the QUICC Engine<sup>&#174;</sup>&#8482; multichannel controller (MCC) and serial interface (SI) of the MPC8360E and MPC8568E can be configured to control 16 E1 or T1 interfaces. None /docs/en/application-note/AN3536.pdf English documents 538307 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3536.pdf Enhanced Serial Interface Mapping: 16 E1/T1 QUICC Engine<sup>&#174;</sup>&#8482; Solution for TDM Connectivity /docs/en/application-note/AN3536.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N Enhanced Serial Interface Mapping: 16 E1/T1 QUICC Engine<sup>&#174;</sup>&#8482; Solution for TDM Connectivity 538.3 KB AN3536 N 1194627746614711196965 /docs/en/application-note/AN3445.pdf 2016-10-31 1194389310604697206738 PSP 36 Oct 31, 2007 Application Note AN3445: This application note outlines general, high-level, architectural differences between the e300 and e500 family processors. The e300 family (which are based on the original 603 design) was designed to the original PowerPC architecture definition. The e500v1 and e500v2 processors are designed to what was originally the PowerPC Book E architecture and NXP?s embedded implementation standards (EIS). None /docs/en/application-note/AN3445.pdf English documents 934951 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3445.pdf AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3445.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes 935.0 KB AN3445 N 1194389310604697206738 /docs/en/application-note/AN3531.pdf 2016-10-31 1194389312415718217914 PSP 37 Oct 31, 2007 Application Note AN3531: This application note outlines general, high-level, architectural differences between the e600 and e500 family processors. Is intended as a general guideline for programmers and system designers who are assessing the efforts required in migrating to e500-based devices. None /docs/en/application-note/AN3531.pdf English documents 961596 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3531.pdf AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3531.pdf documents 645036621402383989 Application Note N en None pdf 0 N N AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes 961.6 KB AN3531 N 1194389312415718217914 /docs/en/application-note/AN2910.pdf 2016-10-31 1128961595061725581551 PSP 38 Mar 27, 2007 Application Note These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. None /docs/en/application-note/AN2910.pdf English documents 619650 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2910.pdf Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf documents 645036621402383989 Application Note N en None pdf 2 N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces 619.7 KB AN2910 N 1128961595061725581551 /docs/en/application-note/AN3088.pdf 2007-02-15 1171553356793694633748 PSP 39 Feb 15, 2007 Application Note This document reviews the use of Ethernet and RapidIO as a system interconnect fabric, comparing them against the requirements for such fabrics. Quantitative analysis is presented where possible. None /docs/en/application-note/AN3088.pdf English documents 784203 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3088.pdf System Interconnect Fabrics: Ethernet Versus RapidIO /docs/en/application-note/AN3088.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N System Interconnect Fabrics: Ethernet Versus RapidIO 784.2 KB AN3088 N 1171553356793694633748 /docs/en/application-note/AN2540.pdf 2003-07-03 1057245101474727053067 PSP 40 Nov 8, 2006 Application Note The architecture for the PowerPC&#8482; instruction set provides two types of synchronizing instructions:&#13;&#10;* Context-synchronizing&#13;&#10;* Execution-synchronizing &#13;&#10;This application note presents a high-level definition and description of each type of synchronizing instruction. None /docs/en/application-note/AN2540.pdf English documents 451663 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2540.pdf Synchronizing Instructions for PowerPC(TM) Instruction Set Architecture /docs/en/application-note/AN2540.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N Synchronizing Instructions for PowerPC(TM) Instruction Set Architecture 451.7 KB AN2540 N 1057245101474727053067 /docs/en/application-note/AN2932.pdf 2005-12-02 1133538491299733535557 PSP 41 Dec 2, 2005 Application Note This document provides guidelines for basic use of the PowerQUICC<sup>&#174;</sup> III serial RapidIO interface. None /docs/en/application-note/AN2932.pdf English documents 1052512 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2932.pdf Serial RapidIO Bring-Up Procedure on PowerQUICC<sup>&#174;</sup> III /docs/en/application-note/AN2932.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N Serial RapidIO Bring-Up Procedure on PowerQUICC<sup>&#174;</sup> III 1.1 MB AN2932 N 1133538491299733535557 /docs/en/application-note/AN2923.pdf 2005-09-19 1127154752940725970276 PSP 42 Sep 19, 2005 Application Note This application note is provided to assist those engineers wishing to use the serial RapidIO message unit on the PowerQUICC<sup>&#174;</sup>&#8482; III. It summarizes the features and uses of the RapidIO messaging unit (including data messages, doorbell messages and inbound port-writes) and provides example code. These extracted code segments are part of a simple application, written to run on top of U-Boot, to prove the functionality of the messaging unit. None /docs/en/application-note/AN2923.pdf English documents 530575 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2923.pdf Using the Serial RapidIO Messaging Unit on PowerQUICC<sup>&#174;</sup> III /docs/en/application-note/AN2923.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N Using the Serial RapidIO Messaging Unit on PowerQUICC<sup>&#174;</sup> III 530.6 KB AN2923 N 1127154752940725970276 /docs/en/application-note/AN2491.pdf 2003-09-30 1064950886097724682016 PSP 43 Sep 30, 2003 Application Note Simplified Mnemonics for PowerPC Instructions. None /docs/en/application-note/AN2491.pdf English documents 1379878 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2491.pdf Simplified Mnemonics for PowerPC Instructions /docs/en/application-note/AN2491.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N Simplified Mnemonics for PowerPC Instructions 1.4 MB AN2491 N 1064950886097724682016 Application Note Software 4 /secured/assets/documents/en/application-note-software/AN4026SW.zip 2016-10-31 1261066595823727647254 PSP 45 Dec 18, 2009 Application Note Software This is a software demonstration of HDLC mode via a TDM interface using on-chip loopback. The demonstration software in this application note were developed and verified using the MPC8360E&#13;&#10;device in a MPC8360E-RDK system. This note applies to any MPC83xx or MPC85xx device with a QUICC Engine<sup>&#174;</sup> block, although small differences in device and system configuration will require minor changes to the software. Registration With Click-Thru Software Licensing Agreement /secured/assets/documents/en/application-note-software/AN4026SW.zip English documents 26724 1395958162559706127527 789425793691620447 2022-12-07 Y /webapp/Download?colCode=AN4026SW&appType=license Software to accompany application note AN4026. /secured/assets/documents/en/application-note-software/AN4026SW.zip documents 789425793691620447 Application Note Software N en Extended zip 1 Y N Software to accompany application note AN4026. 26.7 KB AN4026SW N 1261066595823727647254 /secured/assets/documents/en/application-note-software/AN3966SW.zip 2016-10-31 1258066894053701788655 PSP 46 Nov 10, 2009 Application Note Software Registration With Click-Thru Software Licensing Agreement /secured/assets/documents/en/application-note-software/AN3966SW.zip English documents 330857 1395958162559706127527 789425793691620447 2022-12-07 Y /webapp/Download?colCode=AN3966SW&appType=license Software to accompany application note AN3966 /secured/assets/documents/en/application-note-software/AN3966SW.zip documents 789425793691620447 Application Note Software N en Extended zip 0 Y N Software to accompany application note AN3966 330.9 KB AN3966SW N 1258066894053701788655 /docs/en/application-note-software/AN3372.pdf 2016-10-31 1181767584945705509512 PSP 47 Jun 13, 2007 Application Note Software This application note addresses a common challenge encountered during circuit board testing with some of the newer NXP microprocessors. It is common practice for board testing houses to test for shorts on the power rails by measuring the resistance from a power rail to the ground rail. In older technologies, this is a reasonable approach. However, this application note explains why this approach can be problematic when used with devices in newer technologies. None /docs/en/application-note-software/AN3372.pdf English documents 163681 None 789425793691620447 2022-12-07 /docs/en/application-note-software/AN3372.pdf Challenges in Testing for Power Rail Shorts with New Technologies /docs/en/application-note-software/AN3372.pdf documents 789425793691620447 Application Note Software N en None pdf 0 N Challenges in Testing for Power Rail Shorts with New Technologies 163.7 KB AN3372 N 1181767584945705509512 /secured/assets/documents/en/application-note-software/AN2810SW.zip 2005-04-14 1113503860374718430905 PSP 48 Aug 15, 2006 Application Note Software AN2810, PowerQUICC<sup>&#174;</sup> UPM Configuration, PowerQUICC, Universal Programmable Machine, Configuration, Application Note Registration With Click-Thru Software Licensing Agreement /secured/assets/documents/en/application-note-software/AN2810SW.zip English documents 5555 1395958162559706127527 789425793691620447 2022-12-07 Y /webapp/Download?colCode=AN2810SW&appType=license AN2810 Supporting Files /secured/assets/documents/en/application-note-software/AN2810SW.zip documents 789425793691620447 Application Note Software N en Extended zip 2 Y N AN2810 Supporting Files 5.6 KB AN2810SW N 1113503860374718430905 Data Sheet 1 /docs/en/data-sheet/MPC8568EEC.pdf 2009-05-06 1241646067662723530655 PSP 1 Oct 25, 2010 Data Sheet Due to feature similarities, this document covers both the MPC8568E and MPC8567E features. None /docs/en/data-sheet/MPC8568EEC.pdf English documents 1483930 None 980000996212993340 2022-12-07 /docs/en/data-sheet/MPC8568EEC.pdf MPC8568E/MPC8567E PowerQUICC<sup>&#174;</sup> III Integrated Processor Hardware Specifications - Data Sheet /docs/en/data-sheet/MPC8568EEC.pdf documents 980000996212993340 Data Sheet N en None Y pdf 1 N MPC8568E/MPC8567E PowerQUICC<sup>&#174;</sup> III Integrated Processor Hardware Specifications - Data Sheet 1.5 MB MPC8568EEC N 1241646067662723530655 Package Information 2 /docs/en/package-information/FC-PBGAPRES.pdf 2016-10-31 1273780789511716723050 PSP 49 Jul 8, 2015 Package Information This document is a presentation on understanding the FC-PBGA package. None /docs/en/package-information/FC-PBGAPRES.pdf English documents 5219387 None 302435339416912908 2022-12-07 N /docs/en/package-information/FC-PBGAPRES.pdf Flip Chip Plastic Ball Grid Array (FC-PBGA) Presentation /docs/en/package-information/FC-PBGAPRES.pdf documents 302435339416912908 Package Information N en None pdf 1 N N Flip Chip Plastic Ball Grid Array (FC-PBGA) Presentation 5.2 MB FC-PBGAPRES N 1273780789511716723050 /docs/en/package-information/MPC8568FLOTHERM.zip 2016-10-31 1208190321586716421830 PSP 50 Apr 13, 2008 Package Information None /docs/en/package-information/MPC8568FLOTHERM.zip English documents 2036 None 302435339416912908 2022-12-07 N /docs/en/package-information/MPC8568FLOTHERM.zip MPC8568E PowerQUICC™ III Thermal Simulation Report and Models /docs/en/package-information/MPC8568FLOTHERM.zip documents 302435339416912908 Package Information N en None Y zip 0 N N MPC8568E PowerQUICC™ III Thermal Simulation Report and Models 2.0 KB MPC8568FLOTHERM N 1208190321586716421830 Product Brief 1 /docs/en/product-brief/MPC8568EPB.pdf 2006-10-10 1160508756184714843480 PSP 51 Sep 29, 2006 Product Brief This document provides an overview of features and functionality of the MPC8568E PowerQUICC<sup>&#174;</sup> III &#8482; integrated communications processor. The MPC8568E offers an excellent combination of protocol and interface support including interworking, a high performance PowerPC CPU with a large L2 cache, a DDR memory controller, and high-speed interfaces such as serial RapidIO and PCI Express. None /docs/en/product-brief/MPC8568EPB.pdf English documents 572903 None 899114358132306053 2022-12-07 /docs/en/product-brief/MPC8568EPB.pdf MPC8568E Integrated Processor - Product Brief /docs/en/product-brief/MPC8568EPB.pdf documents 899114358132306053 Product Brief N en None Y pdf 0 N MPC8568E Integrated Processor - Product Brief 572.9 KB MPC8568EPB N 1160508756184714843480 Reference Manual 6 /secured/assets/documents/en/reference-manual/QEIWRM.pdf 2016-10-31 1233608188787709580857 PSP 2 May 3, 2018 Reference Manual This QEIWRM reference manual defines the functionality of the QUICC Engine<sup>&#174;</sup> block, a versatile RISC-based communication processor. The QUICC Engine block supports multiple external interfaces and protocols independently from the core processor in an integrated processing device. Use this reference manual in conjunction with your device reference manual to implement the QUICC Engine functionality. Registration without Disclaimer /secured/assets/documents/en/reference-manual/QEIWRM.pdf English documents 13369144 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=QEIWRM QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual /secured/assets/documents/en/reference-manual/QEIWRM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 9 Y N QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual 13.4 MB QEIWRM N 1233608188787709580857 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 2016-10-31 1319210247754725815434 PSP 3 Jun 26, 2014 Reference Manual This reference manual describes the resources defined for the Power ISA embedded environment. Registration without Disclaimer /secured/assets/documents/en/reference-manual/EREF_RM.pdf English documents 10448185 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=EREF_RM EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /secured/assets/documents/en/reference-manual/EREF_RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 1 Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 10.4 MB EREF_RM N 1319210247754725815434 /docs/en/reference-manual/e500CORERMAD.pdf 2016-10-31 1152820363245707387417 PSP 4 Sep 11, 2012 Reference Manual E500CORER: This errata document describes corrections to the PowerPC &#8482; e500 Core Family Reference Manual, Revision 1. None /docs/en/reference-manual/e500CORERMAD.pdf English documents 117856 None 500633505221135046 2022-12-07 N /docs/en/reference-manual/e500CORERMAD.pdf E500CORER, Errata to PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/e500CORERMAD.pdf documents 500633505221135046 Reference Manual N en None pdf 1.2 N N E500CORER, Errata to PowerPC ™ e500 Core Family - Reference Manual 117.9 KB E500CORERMAD N 1152820363245707387417 /docs/en/reference-manual/MPC8568ERMAD.pdf 2008-06-19 1213851222026726287806 PSP 5 Oct 14, 2009 Reference Manual This errata describes corrections to the MPC8568E PowerQUICC<sup>&#174;</sup> III\TM Integrated Processor Family Reference Manual, Revision 1. None /docs/en/reference-manual/MPC8568ERMAD.pdf English documents 543181 None 500633505221135046 2022-12-07 /docs/en/reference-manual/MPC8568ERMAD.pdf Errata to MPC8568E PowerQUICC<sup>&#174;</sup> III\TM Integrated Processor Family Reference Manual, Rev. 1 /docs/en/reference-manual/MPC8568ERMAD.pdf documents 500633505221135046 Reference Manual N en None Y pdf 1.2 N Errata to MPC8568E PowerQUICC<sup>&#174;</sup> III\TM Integrated Processor Family Reference Manual, Rev. 1 543.2 KB MPC8568ERMAD N 1213851222026726287806 /docs/en/reference-manual/MPC8568ERM.pdf 2007-10-15 1192477849364736022926 PSP 6 Jun 6, 2008 Reference Manual This reference manual defines the functionality of the MPC8568E. This device integrates a processor core based on Power Architecture &#8482; technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The e500v2 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the Power Architecture technology. None /docs/en/reference-manual/MPC8568ERM.pdf English documents 12765397 None 500633505221135046 2022-12-07 /docs/en/reference-manual/MPC8568ERM.pdf MPC8568E PowerQUICC<sup>&#174;</sup> &#8482; III Integrated Processor Family - Reference Manual /docs/en/reference-manual/MPC8568ERM.pdf documents 500633505221135046 Reference Manual N en None Y pdf 1 N MPC8568E PowerQUICC<sup>&#174;</sup> &#8482; III Integrated Processor Family - Reference Manual 12.8 MB MPC8568ERM N 1192477849364736022926 /docs/en/reference-manual/E500CORERM.pdf 2016-10-31 111qmdXB PSP 7 May 11, 2005 Reference Manual The primary objective of this user&#8217;s manual is to describe the functionality of the e500 embedded microprocessor core for software and hardware developers. The e500 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the PowerPC architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words in the 64-bit general-purpose registers (GPRs). None /docs/en/reference-manual/E500CORERM.pdf English documents 5707515 None 500633505221135046 2022-12-07 /docs/en/reference-manual/E500CORERM.pdf PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/E500CORERM.pdf documents 500633505221135046 Reference Manual N en None pdf 1 N PowerPC ™ e500 Core Family - Reference Manual 5.7 MB E500CORERM N 111qmdXB Supporting Information 2 /docs/en/supporting-information/FSLNISTCAVP.pdf 2016-11-09 1368836090577704535160 PSP 52 Oct 28, 2016 Supporting Information FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. None /docs/en/supporting-information/FSLNISTCAVP.pdf English documents 303546 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1.9 N N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 303.5 KB FSLNISTCAVP N 1368836090577704535160 /docs/en/supporting-information/MPC8568EFAMPECI.pdf 2016-10-31 1232680176147728092093 PSP 53 Dec 10, 2010 Supporting Information Customer Export Control Information Document None /docs/en/supporting-information/MPC8568EFAMPECI.pdf English documents 215247 None 371282830530968666 2023-06-19 N /docs/en/supporting-information/MPC8568EFAMPECI.pdf MPC8568 Family Customer Export Control Information /docs/en/supporting-information/MPC8568EFAMPECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 2 N N MPC8568 Family Customer Export Control Information 215.2 KB MPC8568EFAMPECI N 1232680176147728092093 User Guide 1 /docs/en/user-guide/MPC8568EMDSPBKCG.pdf 2008-03-06 1204820320338725985861 PSP 44 Feb 29, 2008 User Guide This document explains how to use each component of the MPC8568E-MDS-PB modular&#13;&#10;development kit. None /docs/en/user-guide/MPC8568EMDSPBKCG.pdf English documents 1201512 None 132339537837198660 2023-06-18 /docs/en/user-guide/MPC8568EMDSPBKCG.pdf MPC8568E Development Kit Kit Configuration Guide /docs/en/user-guide/MPC8568EMDSPBKCG.pdf documents 132339537837198660 User Guide N en None Y pdf 0 N MPC8568E Development Kit Kit Configuration Guide 1.2 MB MPC8568EMDSPBKCG N 1204820320338725985861 true Y Products

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