Layerscape® 2085A | NXP Semiconductors

Layerscape® 2085A and 2045A Multicore Communications Processors

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Comparison Table

LS2085A LS2045A
Cores 8 4
CPU A57, up to 2.0 GHz/L2 Cache (MB) 8/4 4/2
Packet Processing Accelerator 20 Mp/s (four look-up stages)
LS2 Switch 88 Gb/s

We recommend the following Quad Port Gigabit Copper EEE PHY

F104S8A F104X8A
Description QSGMII PHY Standard Temperature QSGMII PHY Extended Temperature
Operating Temperature (°C) 0 - 125 -40 - 125
Package Type 12x12, QFN, 138-pin, 0.65mm pin pitch 12x12, QFN, 138-pin, 0.65mm pin pitch
Read More Product Detail
N true 0 PSPLS2085Aen 12 Application Note Application Note t789 7 Fact Sheet Fact Sheet t523 1 Product Brief Product Brief t532 1 Supporting Information Supporting Information t531 2 White Paper White Paper t530 1 en_US 1 1 4 English The LS2 family of processors delivers unprecedented performance and integration for the smarter, more capable networks of tomorrow. The LS2 multicore processors combine six Arm&#174; Cortex&#174;- A57 cores and four Cortex-A53 cores with the advanced, high-performance datapath and network peripheral interfaces required for networking, telecom/datacom, wireless infrastructure, military and aerospace applications. 1395939951070700586721 PSP 153.0 KB None None documents None 1395939951070700586721 /docs/en/fact-sheet/LS2FAMILYFS.pdf 152975 /docs/en/fact-sheet/LS2FAMILYFS.pdf LS2FAMILYFS N N 2016-10-31 NXP<sup>®</sup> Rebrand LS2085 Fact Sheet /docs/en/fact-sheet/LS2FAMILYFS.pdf /docs/en/fact-sheet/LS2FAMILYFS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 pdf N en Feb 18, 2020 Fact Sheet t523 Fact Sheet Fact Sheet Y N NXP<sup>®</sup> Rebrand LS2085 Fact Sheet false en_US en Application Note Application Note 7 2 0 Chinese AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ<sup>&#174;</sup> platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105zh PSP 1.0 MB None None documents None 1456317293250700197105 /docs/zh/application-note/AN5260.pdf 1027928 /docs/zh/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/zh/application-note/AN5260.pdf /docs/zh/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 zh Feb 24, 2016 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 1 English AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105 PSP 1.0 MB None None documents None 1456317293250700197105 /docs/en/application-note/AN5260.pdf 1027928 /docs/en/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf /docs/en/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 30, 2020 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 3 0 English This application note describes how to access a serial NAND and an SPISTACK device (serial NOR + serial NAND) as well as boot from it. 1506408477909683742994 PSP 359.4 KB Registration without Disclaimer None documents Extended 1506408477909683742994 /secured/assets/documents/en/application-note/AN5376.pdf 359433 /secured/assets/documents/en/application-note/AN5376.pdf AN5376 documents Y N 2017-09-25 AN5376, How Does QuadSPI Work with a Serial NAND - Application Note /webapp/Download?colCode=AN5376 /secured/assets/documents/en/application-note/AN5376.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Sep 26, 2017 645036621402383989 Application Note Y N AN5376, How Does QuadSPI Work with a Serial NAND - Application Note 4 0 English AN5199: This document targets customers familiar with DPAA1 who would like to know more about DPAA2 before migrating to DPAA2 enabled devices. 1450813697769731607959 PSP 922.3 KB Registration without Disclaimer None documents Extended 1450813697769731607959 /secured/assets/documents/en/application-note/AN5199.pdf 922254 /secured/assets/documents/en/application-note/AN5199.pdf AN5199 documents Y N 2016-10-31 AN5199, Key Concepts for the Transition from DPAA1 to DPAA2 - Application Note /webapp/Download?colCode=AN5199 /secured/assets/documents/en/application-note/AN5199.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Dec 22, 2015 645036621402383989 Application Note Y N AN5199, Key Concepts for the Transition from DPAA1 to DPAA2 - Application Note 5 0 English AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. 1441302193437732651194 PSP 566.4 KB None None documents None 1441302193437732651194 /docs/en/application-note/AN5125.pdf 566365 /docs/en/application-note/AN5125.pdf AN5125 documents N N 2016-10-31 AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf /docs/en/application-note/AN5125.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Sep 3, 2015 645036621402383989 Application Note Y N AN5125, Introduction to Device Trees - Application Note 6 6 English AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. 1264793052715706871063 PSP 547.7 KB Registration without Disclaimer None documents Extended 1264793052715706871063 /secured/assets/documents/en/application-note/AN3940.pdf 547662 /secured/assets/documents/en/application-note/AN3940.pdf AN3940 documents Y N 2016-10-31 AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /webapp/Download?colCode=AN3940 /secured/assets/documents/en/application-note/AN3940.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Nov 25, 2013 645036621402383989 Application Note Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 7 Rev. 0 English This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. 1305312143395731535528 PSP 577.2 KB Registration without Disclaimer None documents Extended 1305312143395731535528 /secured/assets/documents/en/application-note/AN4311.pdf 577164 /secured/assets/documents/en/application-note/AN4311.pdf AN4311 documents Y N 2016-10-31 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /webapp/Download?colCode=AN4311 /secured/assets/documents/en/application-note/AN4311.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 13, 2011 645036621402383989 Application Note Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 8 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939 /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors Product Brief Product Brief 1 9 0 English LS2085APB: This document provides a summary of the LS2085A processor. 1438009483933706765148 PSP 545.8 KB Registration without Disclaimer None documents Extended 1438009483933706765148 /secured/assets/documents/en/product-brief/LS2085APB.pdf 545756 /secured/assets/documents/en/product-brief/LS2085APB.pdf LS2085APB documents Y N 2016-10-31 LS2085APB, LS2085A Processor Product Brief - Product Brief /webapp/Download?colCode=LS2085APB /secured/assets/documents/en/product-brief/LS2085APB.pdf Product Brief N 899114358132306053 2023-06-18 pdf Y en Jul 27, 2015 899114358132306053 Product Brief Y N LS2085APB, LS2085A Processor Product Brief - Product Brief Supporting Information Supporting Information 2 10 1.9 English FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. 1368836090577704535160 PSP 303.5 KB None None documents None 1368836090577704535160 /docs/en/supporting-information/FSLNISTCAVP.pdf 303546 /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP documents N N 2016-11-09 FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf /docs/en/supporting-information/FSLNISTCAVP.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 28, 2016 371282830530968666 Supporting Information Y N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 11 1 English 1475686554793741140074 PSP 19.0 KB None None documents None 1475686554793741140074 /docs/en/supporting-information/LS2085A_80A-PECI.pdf 18972 /docs/en/supporting-information/LS2085A_80A-PECI.pdf LS2085A_80A-PECI documents N N 2016-11-09 LS2085A_80A Family Customer Export Control Information /docs/en/supporting-information/LS2085A_80A-PECI.pdf /docs/en/supporting-information/LS2085A_80A-PECI.pdf Supporting Information N 371282830530968666 2023-06-19 pdf N en Oct 5, 2016 371282830530968666 Supporting Information Y N LS2085A_80A Family Customer Export Control Information White Paper White Paper 1 12 0 English QORIQPMWP: This document describes how Power Management technologies will play a more important role in controlling or reducing power consumption of electronic systems. 1419964678458711207150 PSP 1.4 MB None None documents None 1419964678458711207150 /docs/en/white-paper/QORIQPMWP.pdf 1418055 /docs/en/white-paper/QORIQPMWP.pdf QORIQPMWP documents N N 2017-03-30 QORIQPMWP, QorIQ Power Management - White Paper /docs/en/white-paper/QORIQPMWP.pdf /docs/en/white-paper/QORIQPMWP.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Mar 30, 2017 918633085541740938 White Paper N QORIQPMWP, QorIQ Power Management - White Paper false 0 LS2085A downloads en true 1 Y PSP Application Note 7 /docs/en/application-note/AN5260.pdf 2016-10-31 1456317293250700197105 PSP 2 Nov 30, 2020 Application Note AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). None /docs/en/application-note/AN5260.pdf English documents 1027928 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5260.pdf PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N PBL Configuration using QCVS Application Note 1.0 MB AN5260 N 1456317293250700197105 /secured/assets/documents/en/application-note/AN5376.pdf 2017-09-25 1506408477909683742994 PSP 3 Sep 26, 2017 Application Note This application note describes how to access a serial NAND and an SPISTACK device (serial NOR + serial NAND) as well as boot from it. Registration without Disclaimer /secured/assets/documents/en/application-note/AN5376.pdf English documents 359433 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN5376 AN5376, How Does QuadSPI Work with a Serial NAND - Application Note /secured/assets/documents/en/application-note/AN5376.pdf documents 645036621402383989 Application Note N en Extended Y pdf 0 Y N AN5376, How Does QuadSPI Work with a Serial NAND - Application Note 359.4 KB AN5376 N 1506408477909683742994 /secured/assets/documents/en/application-note/AN5199.pdf 2016-10-31 1450813697769731607959 PSP 4 Dec 22, 2015 Application Note AN5199: This document targets customers familiar with DPAA1 who would like to know more about DPAA2 before migrating to DPAA2 enabled devices. Registration without Disclaimer /secured/assets/documents/en/application-note/AN5199.pdf English documents 922254 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN5199 AN5199, Key Concepts for the Transition from DPAA1 to DPAA2 - Application Note /secured/assets/documents/en/application-note/AN5199.pdf documents 645036621402383989 Application Note N en Extended Y pdf 0 Y N AN5199, Key Concepts for the Transition from DPAA1 to DPAA2 - Application Note 922.3 KB AN5199 N 1450813697769731607959 /docs/en/application-note/AN5125.pdf 2016-10-31 1441302193437732651194 PSP 5 Sep 3, 2015 Application Note AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. None /docs/en/application-note/AN5125.pdf English documents 566365 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5125.pdf AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N AN5125, Introduction to Device Trees - Application Note 566.4 KB AN5125 N 1441302193437732651194 /secured/assets/documents/en/application-note/AN3940.pdf 2016-10-31 1264793052715706871063 PSP 6 Nov 25, 2013 Application Note AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3940.pdf English documents 547662 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3940 AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /secured/assets/documents/en/application-note/AN3940.pdf documents 645036621402383989 Application Note N en Extended Y pdf 6 Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 547.7 KB AN3940 N 1264793052715706871063 /secured/assets/documents/en/application-note/AN4311.pdf 2016-10-31 1305312143395731535528 PSP 7 May 13, 2011 Application Note This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4311.pdf English documents 577164 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4311 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /secured/assets/documents/en/application-note/AN4311.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev. 0 Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 577.2 KB AN4311 N 1305312143395731535528 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 8 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939 DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 Fact Sheet 1 /docs/en/fact-sheet/LS2FAMILYFS.pdf 2016-10-31 1395939951070700586721 PSP 1 Feb 18, 2020 Fact Sheet Fact Sheet The LS2 family of processors delivers unprecedented performance and integration for the smarter, more capable networks of tomorrow. The LS2 multicore processors combine six Arm&#174; Cortex&#174;- A57 cores and four Cortex-A53 cores with the advanced, high-performance datapath and network peripheral interfaces required for networking, telecom/datacom, wireless infrastructure, military and aerospace applications. None /docs/en/fact-sheet/LS2FAMILYFS.pdf English 152975 None Fact Sheet 2022-12-07 N /docs/en/fact-sheet/LS2FAMILYFS.pdf NXP<sup>®</sup> Rebrand LS2085 Fact Sheet /docs/en/fact-sheet/LS2FAMILYFS.pdf documents 736675474163315314 Fact Sheet N Y en None Y t523 pdf 4 N N NXP<sup>®</sup> Rebrand LS2085 Fact Sheet 153.0 KB LS2FAMILYFS N 1395939951070700586721 Product Brief 1 /secured/assets/documents/en/product-brief/LS2085APB.pdf 2016-10-31 1438009483933706765148 PSP 9 Jul 27, 2015 Product Brief LS2085APB: This document provides a summary of the LS2085A processor. Registration without Disclaimer /secured/assets/documents/en/product-brief/LS2085APB.pdf English documents 545756 None 899114358132306053 2023-06-18 Y /webapp/Download?colCode=LS2085APB LS2085APB, LS2085A Processor Product Brief - Product Brief /secured/assets/documents/en/product-brief/LS2085APB.pdf documents 899114358132306053 Product Brief N en Extended Y pdf 0 Y N LS2085APB, LS2085A Processor Product Brief - Product Brief 545.8 KB LS2085APB N 1438009483933706765148 Supporting Information 2 /docs/en/supporting-information/FSLNISTCAVP.pdf 2016-11-09 1368836090577704535160 PSP 10 Oct 28, 2016 Supporting Information FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. None /docs/en/supporting-information/FSLNISTCAVP.pdf English documents 303546 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1.9 N N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 303.5 KB FSLNISTCAVP N 1368836090577704535160 /docs/en/supporting-information/LS2085A_80A-PECI.pdf 2016-11-09 1475686554793741140074 PSP 11 Oct 5, 2016 Supporting Information None /docs/en/supporting-information/LS2085A_80A-PECI.pdf English documents 18972 None 371282830530968666 2023-06-19 N /docs/en/supporting-information/LS2085A_80A-PECI.pdf LS2085A_80A Family Customer Export Control Information /docs/en/supporting-information/LS2085A_80A-PECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1 N N LS2085A_80A Family Customer Export Control Information 19.0 KB LS2085A_80A-PECI N 1475686554793741140074 White Paper 1 /docs/en/white-paper/QORIQPMWP.pdf 2017-03-30 1419964678458711207150 PSP 12 Mar 30, 2017 White Paper QORIQPMWP: This document describes how Power Management technologies will play a more important role in controlling or reducing power consumption of electronic systems. None /docs/en/white-paper/QORIQPMWP.pdf English documents 1418055 None 918633085541740938 2023-06-19 N /docs/en/white-paper/QORIQPMWP.pdf QORIQPMWP, QorIQ Power Management - White Paper /docs/en/white-paper/QORIQPMWP.pdf documents 918633085541740938 White Paper N en None pdf 0 N N QORIQPMWP, QorIQ Power Management - White Paper 1.4 MB QORIQPMWP N 1419964678458711207150 true Y Products

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