Design Files
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- No Longer Manufactured
- P87C51SBAA
80C51 8-Bit Microcontroller Family
The Philips 80C51/87C51/80C52/87C52 is a high-performance static 80C51 design fabricated with Philips high-density CMOS technology with operation from 2.7 V to 5.5 V.
The 8xC51 and 8xC52 contain a 128 bytes RAM and 256 bytes RAM respectively, 32 I/O lines, three 16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits.
In addition, the device is a low power static design which offers a wide range of operating frequencies down to zero. Two software selectable modes of power reduction-idle mode and power-down mode are available. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. Since the design is static, the clock can be stopped without loss of user data and then the execution resumed from the point the clock was stopped.
Outline 3d SOT187-2
Product Details
Block Diagram
Features
- 8051 Central Processing Unit
- 4k ? 8 ROM (80C51)
- 8k ? 8 ROM (80C52)
- 128 ? 8 RAM (80C51)
- 256 ? 8 RAM (80C52)
- Three 16-bit counter/timers
- Boolean processor
- Full static operation
- Low voltage (2.7 V to 5.5 V@ 16 MHz) operation
- Memory addressing capability
- 64k ROM and 64k RAM
- Power control modes:
- Clock can be stopped and resumed
- Idle mode
- Power-down mode
- CMOS and TTL compatible
- TWO speed ranges at VCC = 5 V
- 0 to 16 MHz
- 0 to 33 MHz
- Three package styles
- Extended temperature ranges
- Dual Data Pointers
- Security bits:
- ROM (2 bits)
- OTP/EPROM (3 bits)
- Encryption array - 64 bytes
- 4 level priority interrupt
- 6 interrupt sources
- Four 8-bit I/O ports
- Full-duplex enhanced UART
- Framing error detection
- Automatic address recognition
- Programmable clock out
- Asynchronous port reset
- Low EMI (inhibit ALE and slew rate controlled outputs)
- Wake-up from Power Down by an external interrupt
Buy/Parametrics
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Documentation
Quick reference to our documentation types.
1-5 of 16 documents
-
Application Note
PCA9564 Evaluation Board
-
Application Note
PCA9564 - I²C-Bus Controller - Application Note
-
Application Note
AN96022
