24-bit General Embedded DSP

DSP56321 Not Recommended for New Designs
  • This page contains information on a product that is not recommended for new designs.

The DSP56321, a member of the DSP56300 family of programmable DSPs, supports network applications with general filtering operations. The on-chip enhanced filter coprocessor (EFCOP) executes filter algorithms in parallel with core operations to provide enhanced signal quality without affecting channel throughput or total number of channels supported, resulting in increased overall performance. Like the other family members, the DSP56321 uses a high-performance, single clock cycle per instruction engine, a barrel shifter, 24-bit addressing, instruction cache, and direct memory access (DMA) controller. The DSP56321 offers 275 million multiply accumulates per second (MMACS) performance (550 MMACS using the EFCOP in filtering applications) using an internal 275 MHz clock, a 1.6-volt core and independent 3.3-volt input/output (I/O).

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Product Details

Block Diagram

DSP56321 Block Diagram

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Features

  • 275 MMACS (550 MMACS using the EFCOP in filtering applications) with a 275 MHz clock at 1.6 volts
  • Object code compatible with the DSP56000 core with highly parallel instruction set
  • Data arithmetic logic unit (data ALU) with fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions and 24-bit or 16-bit arithmetic support under software control
  • Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for DSP applications (including immediate offsets), on-chip instruction cache controller, on-chip memory-expandable hardware stack, nested hardware DO loops and fast auto-return interrupts
  • DMA with six channels supporting internal and external accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-of-block- transfer interrupts; and triggering from interrupt lines and all peripherals
  • Digital phase-lock loop (DPLL) allows change of low-power divide factor (DF) without loss of lock
  • Hardware debugging support including on-chip emulation (OnCE) module, JTAG test access port (TAP)
  • Internal 24 x 24-bit filtering and echo-cancellation coprocessor
  • Runs in parallel to the DSP core
  • 192K x 24-bit on-chip RAM total
  • Program RAM, instruction cache, X data RAM and Y data RAM sizes are programmable:
    Program
    RAM Size
    Instruction
    Cache Size
    X Data
    RAM Size*
    Y Data
    RAM Size*
    32 K x 24-bit
    0
    80 K x 24-bit
    80 K x 24-bit
    31 K x 24-bit
    1024 x 24-bit
    80 K x 24-bit
    80 K x 24-bit
    40 K x 24-bit
    0
    76 K x 24-bit
    76 K x 24-bit
    39 K x 24-bit
    1024 x 24-bit
    76 K x 24-bit
    76 K x 2 4-bit
    48 K x 24-bit
    0
    72 K x 24-bit
    72 K x 24-bit
    47 K x 24-bit
    1024 x 24-bit
    72 K x 24-bit
    72 K x 24-bit
    64 K x 24-bit
    0
    64 K x 24-bit
    64 K x 24-bit
    63 K x 24-bit
    1024 x 24-bit
    64 K x 24-bit
    64 K x 24-bit
    72 K x 24-bit
    0
    60 K x 24-bit
    60 K x 24-bit
    71 K x 24-bit
    1024 x 24-bit
    60 K x 24-bit
    60 K x 24-bit
    80 K x 24-bit
    0
    56 K x 24-bit
    56 K x 24-bit
    79 K x 24-bit
    1024 x 24-bit
    56 K x 24-bit
    56 K x 24-bit
    96 K x 24-bit
    0
    48 K x 24-bit
    48 K x 24-bit
    95 K x 24-bit
    1024 x 24-bit
    48 K x 24-bit
    48 K x 24-bit
    112 K x 24-bit
    0
    40 K x 24-bit
    40 K x 24-bit
    111 K x 24-bit
    1024 x 24-bit
    40 K x 24-bit
    40 K x 24-bit
    * Includes 12 K x 24-bit shared memory (that is, memory shared by the core and the EFCOP).
  • 192 x 24-bit bootstrap ROM
  • Up to two 256K x 24-bit word memory spaces using the standard external address lines
  • Program memory expansion to one 256K x 24-bit word memory space using the standard external address lines
  • External memory expansion port
  • Chip select logic for glueless interface to SRAMs
  • 3.3-volt I/O interface enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides glueless connection to a number of industry-standard microcomputers, microprocessors and DSPs
  • Two enhanced synchronous serial interfaces (ESSI0 and ESSI1), each with one receiver and three transmitters
  • Serial communications interface (SCI) with baud-rate generator
  • Triple timer module
  • Up to 34 programmable general-purpose I/O (GPIO) signals, depending on which peripherals are enabled
  • Very low-power CMOS design
  • Wait and stop low-power standby modes
  • Fully static design specified to operate down to 0 Hz (DC)
  • Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent)

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